Abstract:
A baseband processing module includes an RX interface, a rake receiver combiner module, and may include additional components. The RX interface receives the baseband signals from an RF front end and creates baseband RX signal samples there from. The rake receiver combiner module includes control logic, an input buffer, a rake despreader module, and an output buffer. The rake despreader module is operable to despread the baseband RX signal samples in a time divided fashion to produce channel symbols including pilot channel symbols and physical channel symbols.
Abstract:
A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. In another embodiment, a communication device having a system acquisition function is provided which includes the system acquisition module and a receiver configured to receive signals, where a plurality of configurable computational units are selectively configurable to implement the PN sequence generator.
Abstract:
A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.
Abstract:
Searcher hardware is multiplexed to perform simultaneous searches in either an IS-95 CDMA mode or a GPS mode. In the IS-95 mode, the search hardware is time-multiplexed into a number of searcher time slices, each of which can generate a PN sequence to despread a data sequence. In the GPS mode, the search hardware is configured as a number of distinct GPS channels, each of which can generate a Gold code sequence for tracking a GPS signal from a particular GPS satellite. This configuration allows the searcher to perform multiple GPS signal searches simultaneously. Signal searching in both IS-95 and GPS modes is performed at significantly higher speeds compared to conventional searcher hardware. Moreover, the search hardware can be dynamically configured to operate in either the IS-95 or the GPS mode, eliminating the need for dedicated circuitry for each mode of operation.
Abstract:
A configurable all-digital coherent demodulator system for spread spectrum digital communications is disclosed herein. The demodulator system includes an extended and long code demodulator (ELCD) coupled to a traffic channel demodulator (TCD) and a parameter estimator (PE). The demodulator also includes a pilot assisted correction device (PACD) that is coupled to the PE and the TCD. The ELCD provides a code-demodulated signal to the TCD and the PE. In turn, the TCD provides a demodulated output data signal to the PE. The PACD corrects the phase error of the demodulated output data based on an error estimate that is fed forward from the PE. Accumulation operations in the ELCD, TCD, and PE are all programmable. Similarly, a phase delay in the PACD is also programmable to provide synchronization with the error estimate from the PE.
Abstract:
Searcher hardware is multiplexed to perform simultaneous searches in either an IS-95 CDMA mode or a GPS mode. In the IS-95 mode, the search hardware is time-multiplexed into a number of searcher time slices, each of which can generate a PN sequence to despread a data sequence. In the GPS mode, the search hardware is configured as a number of distinct GPS channels, each of which can generate a Gold code sequence for tracking a GPS signal from a particular GPS satellite. This configuration allows the searcher to perform multiple GPS signal searches simultaneously. Signal searching in both IS-95 and GPS modes is performed at significantly higher speeds compared to conventional searcher hardware. Moreover, the search hardware can be dynamically configured to operate in either the IS-95 or the GPS mode, eliminating the need for dedicated circuitry for each mode of operation.
Abstract:
A baseband processing module includes an RX interface, a rake receiver combiner module, and may include additional components. The RX interface receives the baseband signals from an RF front end and creates baseband RX signal samples there from. The rake receiver combiner module includes control logic, an input buffer, a rake despreader module, and an output buffer. The rake despreader module is operable to despread the baseband RX signal samples in a time divided fashion to produce channel symbols including pilot channel symbols and physical channel symbols.
Abstract:
In a method of interference mitigation in a multi user detection capable radio base station in a communication system, which radio base station comprises a set confined detection modules, at least one of which is capable of handling multiple user connections, first and at least a second subset of detection modules are formed from said set, wherein the second set comprises at least one interference mitigation capable detection module. Interference information from the first subset is communicated to the second subset, interference originating in user connections of the first subset are then mitigated from the user connections of the second subset. Subsequently, interference is mutually mitigated between the connections within the interference mitigation capable detection module.
Abstract:
A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. In another embodiment, a communication device having a system acquisition function is provided which includes the system acquisition module and a receiver configured to receive signals, where a plurality of configurable computational units are selectively configurable to implement the PN sequence generator.
Abstract:
An architecture for a wideband code-division multiple access (WCDMA) baseband system is provided. The system comprises separate processing blocks (e.g. cell search, RAKE receiver, transmitter engine, and error correction). Each block comprises a hard-wired logic block and a CSP (communication signal processor). The architecture of each CSP is optimized to perform a particular signal processing function. Each CSP has an associated memory architecture that is optimized for the particular signal processing function. Each memory architecture includes at least two memories that are independently addressable to support simultaneous read and/or write access. The instruction set for each CSP is optimized based on the particular signal processing function. Each instruction set includes instruction words that are optimized for the particular signal processing function. One or more instruction words support simultaneous read/write accesses in parallel.