公开(公告)号：US20030141898A1

公开(公告)日：2003-07-31

申请号：US09924354

申请日：2001-08-07

申请人： Altera Corporation

发明人： Martin Langhammer ,  Nitin Prasad

IPC分类号： H03K019/177

CPC分类号： G06F7/5095 ,  G06F5/015 ,  G06F7/53 ,  G06F7/575 ,  G06F7/724 ,  G06F15/7867 ,  G06F2207/3828 ,  H03K19/177 ,  H03K19/17732 ,  H03K19/17736

摘要： A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (nullFSBnull) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers.

摘要翻译： 可编程逻辑集成电路器件除了可编程逻辑的通常多个区域和通常的可编程逻辑器件之外，还具有至少一个功能特定电路块（例如，并行乘法器，并行桶形移位器，并行算术逻辑单元等） 互联电路资源。 为了减少使用功能特定块（“FSB”）对设备的通用互连资源的影响，FSB的输入和/或输出可以相对直接地耦合到逻辑区域的子集。 除了节省通用互连之外，FSB可以使用FSB连接的逻辑区域的资源，以减少必须专用于FSB的电路的数量。 如果FSB是乘法器，则附加特征包括促进连续乘法器输出的累积（如果需要，使用加法或减法和符号扩展）和/或算术组合多个乘法器的输出。

公开(公告)号：US20030107401A1

公开(公告)日：2003-06-12

申请号：US09927793

申请日：2001-08-10

申请人： LATTICE SEMICONDUCTOR CORPORATION

发明人： Om P. Agrawal ,  Xiaojie (Warren) He ,  Claudia A. Stanley ,  Larry R. Metzger ,  Chong M. Lee

IPC分类号： H03K019/177

CPC分类号： H03K19/1737 ,  H03K19/177

摘要： An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PT's) therefrom. Part or all of the macrocell's local 5 PT's may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoP's generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PT's (e.g., null5 PT's) to having slower generation of sums of a much larger number of PT's (e.g.,

摘要翻译： 改进的高密度CPLD包括多个宏单元部分。 每个宏小区部分可以接收相对大量的独立输入项，并且可以生成至少多达5个不同产品项信号（PT）作为基本簇。 宏单元本地5 PT的部分或全部可用于在本地一级ORring操作中生成本地产品（SoP）产品（SoP）信号。 另外，在相邻宏小区部分中生成的SoP可以被选择性地和递增级联（交叉），以用于对本地SoP信号的补充求和。 可以在用于第二级求和的和共享阵列中进一步选择相邻部分的SoP信号。 第一级级联（交错法）和二级总和共享的组合提供了广泛的可编程选择的粒度，包括相对较快地生成仅几个PT的总和（例如，<= 5PT） 要产生更大数量的PT（例如，<160 PT）的总和的较慢生成。

公开(公告)号：US20030071654A1

公开(公告)日：2003-04-17

申请号：US10299572

申请日：2002-11-18

发明人： James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

IPC分类号： H03K019/177

CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：US20030071653A1

公开(公告)日：2003-04-17

申请号：US10295713

申请日：2002-11-15

申请人： Xilinx, Inc.

发明人： Richard A. Carberry ,  Barbara Dahl ,  Steven P. Young ,  Trevor J. Bauer

IPC分类号： H03K019/177

CPC分类号： H03K19/17728 ,  H03K19/1737

摘要： A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.

摘要翻译： 用于可编程逻辑器件（PLD）的快速，节省空间的查找表（LUT），其中修改LUT的写解码器，读取解码器和存储器块以提供高性能，同时提供高效布局。 写解码器和读取解码器都由LUT输入信号控制，数据信号被直接发送到存储器块的每个存储电路（即不经过写入解码器）。 读取解码器包括由一系列多路复用器组成的复用电路，该多路复用器由从PLD的互连资源接收的输入信号直接控制。 在一个实施例中，可配置逻辑块被提供有由第一LUT和第二LUT共享的单个写入解码器。

公开(公告)号：US20030062923A1

公开(公告)日：2003-04-03

申请号：US09924365

申请日：2001-08-07

申请人： Xilinx, Inc.

发明人： Zhi-Min Ling ,  Jae Cho ,  Robert W. Wells ,  Clay S. Johnson ,  Shelly G. Davis

IPC分类号： H03K019/177

CPC分类号： G01R31/318519

摘要： FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.

摘要翻译： 如果在设计中不使用局部缺陷，则可以使用包含至少一个局部缺陷的FPGA来实现一些设计。 为了确定FPGA是否适合实现设计，该设计被加载到FPGA中。 测试FPGA是否可以准确地执行设计，即使是局部缺陷。 如果通过测试，FPGA将被标记为适合该设计。 如果发现FPGA不适合于一种设计，则可以测试其他设计。 因此，FPGA制造商可以销售通常被丢弃的FPGA。 因此，这些FPGA的价格可能会显着降低。

公开(公告)号：US20030062922A1

公开(公告)日：2003-04-03

申请号：US09968446

申请日：2001-09-28

申请人： Xilinx, Inc.

发明人： Stephen M. Douglass ,  Steven P. Young

IPC分类号： H03K019/177

CPC分类号： G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric.

摘要翻译： 互连逻辑提供嵌入式固定逻辑电路或电路与可编程门阵列的可编程逻辑结构的连接，使得固定逻辑电路用作可编程逻辑结构的扩展。 互连逻辑包括互连瓦片，并且还可以包括接口逻辑。 互连瓦片提供固定逻辑电路的输入和/或输出与可编程逻辑结构的互连之间的选择性连接。 接口逻辑（包含在内）提供逻辑电路，用于对固定逻辑电路和可编程逻辑结构之间的数据传输进行调节。

公开(公告)号：US20020171451A1

公开(公告)日：2002-11-21

申请号：US09467802

申请日：1999-12-20

申请人： FUJITSU LIMITED

发明人： HIROSHI HAMANO ,  TAKUJI YAMAMOTO ,  SATOSHI KUROYANAGI

IPC分类号： H03K019/177

CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/1576 ,  H04L2012/5605 ,  H04Q11/0001 ,  H04Q11/0478 ,  Y10T307/747

摘要： The present invention relates to a technology of a crosspoint switch circuit applied to a cross-connect apparatus, an ADM or the like employed in an optical network. According to the present invention, there is provided an arrangement of a crosspoint switch circuit including a plurality of switch cells arrayed in a matrix fashion to form a matrix array, each of the switch cells being formed of a two-input and two-output type switch having a first and second input terminals and a first and second output terminals in which either of the input terminals is made connectable to any of the output terminals, and each of the switch cells being interconnected and controlled in each connecting status so that any one of input highway is made connectable to any of output highway, and external connecting unit provided on each side of the matrix array so that the switch cells arrayed on each side of the matrix array are made connectable to switch cells arrayed on any side of a matrix array of another crosspoint switch circuit which is to neighbor that crosspoint switch circuit. According to the above arrangement, the crosspoint switch circuit can easily and flexibly respond to a request of extensively increasing the channel size under a minimum space limitation. Moreover, the crosspoint switch circuit can be assembled and manufactured with ease.

摘要翻译： 本发明涉及应用于在光网络中采用的交叉连接装置，ADM等的交叉点开关电路的技术。 根据本发明，提供一种交叉点开关电路的布置，该交叉点开关电路包括以矩阵方式排列的多个开关单元以形成矩阵阵列，每个开关单元由双输入和双输出型 开关具有第一和第二输入端子以及第一和第二输出端子，其中任一个输入端子可连接到任何输出端子，并且每个开关单元在每个连接状态下被互连和控制，使得任何一个 输入公路的连接可连接到输出公路中的任何一个，并且设置在矩阵阵列的每一侧的外部连接单元，使得排列在矩阵阵列的每一侧上的开关单元可连接到矩阵的任何一侧上排列的开关单元 另一个交叉点开关电路的阵列，其邻接该交叉点开关电路。 根据上述结构，交叉点开关电路可以容易且灵活地响应在最小空间限制下广泛增加信道大小的请求。 此外，交叉点开关电路可以容易地组装和制造。

公开(公告)号：US20020163358A1

公开(公告)日：2002-11-07

申请号：US10140911

申请日：2002-05-06

发明人： Brian D. Johnson ,  Andy L. Lee ,  Cameron McClintock ,  Giles V. Powell ,  Paul Leventis

IPC分类号： H03K019/177

CPC分类号： H03K19/17748 ,  H03K19/17732 ,  H03K19/17736

摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be nullpartialnull and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.

摘要翻译： PLD中的路由结构以交错方式实现。 否则将在路由架构边界“部分”和悬挂的路由线被驱动，为从边界向PLD核心路由信号提供了额外的灵活性。

公开(公告)号：US20020130681A1

公开(公告)日：2002-09-19

申请号：US09935792

申请日：2001-08-22

发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. Mc Clintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

IPC分类号： H03K019/177

CPC分类号： H03K19/17736 ,  G01R31/318516 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (nullLABsnull). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

公开(公告)号：US20020070756A1

公开(公告)日：2002-06-13

申请号：US10021744

申请日：2001-12-05

发明人： Benjamins S. Ting ,  Peter M. Pani

IPC分类号： H01L025/00 ,  H03K019/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17792 ,  H03K19/17796

摘要： A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit This floor plan is a scalable block architecture in which each block connector tab networks of a 2null2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions (instead of the typical north, south, east and west directions) such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement enables a 4null4 block grouping to be scalable. The innovative floor plan makes efficient use of die space with little layout dead space as the floor plan provides for a plurality of contiguous memory and passgate arrays (which provide the functionality of the bidirectional switches) with small regions of logic for CFGs and drivers of the block connector tab networks. Therefore, the gaps typically incurred due to a mixture of memory and logic are avoided. Intra-cluster routing lines and bi-directional routing lines are overlayed on different layers of the chip together with memory and passgate arrays to provide connections to higher level routing lines and connections between CFGs in the block.

摘要翻译： 一种可编程逻辑器件，其结合了由多层次的布线线，连接器标签网络和转向矩阵组成的创新路由层次结构，能够在集成电路实现中使用创新的节省空间的平面图，并且当SRAM 用作配置位该平面图是可扩展的块架构，其中将2x2块分组的每个块连接器选项卡网络相对于彼此沿相邻轴线布置为镜像。 此外，双向输入/输出线被提供，因为每个块的输入/输出装置仅在两个方向（而不是典型的北，南，东和西方向）上取向，使得相邻块的块连接器标签网络面向 相互取向。 这种方向和布置允许块共享路由资源。 此外，这种布置使得4×4块分组能够可扩展。 创新的平面图计划有效地利用了具有很小的布局死空间的管芯空间，因为平面图为多个连续的存储器和通孔阵列（其提供双向开关的功能）提供了用于CFG的驱动器的小的逻辑区域 阻止连接器选项卡网络。 因此，避免了由于存储器和逻辑的混合引起的间隙。 集群内路由线路和双向路由线路与芯片的不同层与存储器和传递门阵列重叠，以提供与较高级路由线路的连接以及块中CFG之间的连接。