公开(公告)号：US08059199B2

公开(公告)日：2011-11-15

申请号：US12207520

申请日：2008-09-10

申请人： Takamichi Nakano ,  Ryota Mizoguchi

发明人： Takamichi Nakano ,  Ryota Mizoguchi

IPC分类号： H04N5/10

CPC分类号： H04N5/08

摘要： The present invention provides a synchronizing signal detection circuit capable of always stably detecting a synchronizing signal. The synchronizing signal detection circuit predicts detection positions of synchronizing pulses every synchronization cycle peculiar to an input video signal. The synchronizing signal detection circuit further supplies the input video signal to a plurality of unnecessary signal eliminating paths in common and extracts synchronizing signals of every path respectively from video signals of every path obtained by eliminating unnecessary signals according to the characteristics of the paths every path. Then, the synchronizing signal detection circuit acquires detection positions of synchronizing pulses of the synchronizing signals of every path, selects a synchronizing signal of every path at which a difference in time between each of the detection positions of every path and the predicted detection position is minimal, and sets the selected synchronizing signal as an output synchronizing signal.

摘要翻译： 本发明提供一种能够始终稳定地检测同步信号的同步信号检测电路。 同步信号检测电路对输入视频信号特有的每个同步周期预测同步脉冲的检测位置。 同步信号检测电路还将输入视频信号共同地提供给多个不需要的信号消除路径，并且根据每个路径的路径的特性，分别从每个路径的视频信号中分离出通过消除不必要的信号而获得的每个路径的同步信号。 然后，同步信号检测电路取得各通路的同步信号的同步脉冲的检测位置，选择各通路的检测位置和预测检测位置之间的时间差最小的路径的同步信号 并将所选择的同步信号设置为输出同步信号。

公开(公告)号：US08014452B2

公开(公告)日：2011-09-06

申请号：US10716791

申请日：2003-11-19

申请人： Hiroaki Kubo ,  Masahiro Murakami

发明人： Hiroaki Kubo ,  Masahiro Murakami

IPC分类号： H04N5/04 ,  H04N5/05 ,  H04N5/10 ,  H04N21/8547 ,  H04N7/01 ,  H04M1/00 ,  H04N7/26

CPC分类号： H04N5/4401 ,  H04N5/46 ,  H04N21/4135 ,  H04N21/4305 ,  H04N21/4334 ,  H04N21/434

摘要： A format conversion circuit 100 includes a FIFO memory 101 for writing and reading video data VD in synchronization with a sampling clock CK, a header generation circuit 102 for generating an MPEG2-TS packet header, and a synchronous timing detection circuit 103 for detecting a horizontal synchronizing signal for the video data VD. The format conversion circuit 100 also includes a counter 104 which counts the number of bytes of packet header and the number of bytes of video data VD, and a switch 105 which selects the packet header until the counted number of bytes reaches four bytes, and then selects the video data read out of the FIFO memory 101.

摘要翻译： 格式转换电路100包括用于与采样时钟CK同步地写入和读取视频数据VD的FIFO存储器101，用于生成MPEG2-TS分组报头的报头生成电路102以及用于检测水平的同步定时检测电路103 用于视频数据VD的同步信号。 格式转换电路100还包括计数器104，其计数分组报头的字节数和视频数据VD的字节数;以及开关105，其选择分组报头直到计数的字节数达到四个字节，然后 选择从FIFO存储器101读出的视频数据。

公开(公告)号：US20110074921A1

公开(公告)日：2011-03-31

申请号：US12807967

申请日：2010-09-17

申请人： Hiroshi Takiduka ,  Koichi Takenaka

发明人： Hiroshi Takiduka ,  Koichi Takenaka

IPC分类号： H04N5/10 ,  H04N13/00 ,  H04N7/00

CPC分类号： H04N21/4516 ,  G09G5/006 ,  G09G2370/04 ,  G09G2370/047 ,  G09G2370/12 ,  H04N7/08 ,  H04N13/156 ,  H04N13/161 ,  H04N13/183 ,  H04N13/194 ,  H04N21/4135 ,  H04N21/435 ,  H04N21/43635

摘要： A transmitter includes: a transmission data generation section generating transmission data having a format of video field period as a unit including a horizontal blanking period, a vertical blanking period and an active video period which are separated by vertical synchronization signals, the active video period including a main video area and an auxiliary video area; and a transmission data transmitting section transmitting, in a differential signal format, the transmission data generated in the transmission data generation section to an external device through a transmission path and through a plurality of channels. The transmission data generation section allocates picture data to the main video area and allocates, to the auxiliary video area, additional information relating to the picture data allocated to the main video area.

摘要翻译： 发送机包括：发送数据生成部，其生成具有视频场期间格式的发送数据，该发送数据包括由垂直同步信号分离的水平消隐期间，垂直消隐期间和有效视频期间，所述有效视频期间包括 主视频区和辅助视频区; 以及发送数据发送部，其以差分信号格式，通过发送路径和通过多个信道将在发送数据生成部中生成的发送数据发送到外部设备。 发送数据生成部将图像数据分配给主视频区域，并向辅助视频区域分配与分配给主视频区域的图像数据有关的附加信息。

公开(公告)号：USRE40396E1

公开(公告)日：2008-06-24

申请号：US10131049

申请日：2002-04-25

申请人： Ji-Young Lee

发明人： Ji-Young Lee

IPC分类号： H04N5/04 ,  H04N5/08 ,  H04N5/10

CPC分类号： H04N5/10

摘要： A method for detecting and separating vertical and horizontal synchronous signals from a computer system. The input forms of the vertical and horizontal synchronous signals from the computer system are detected by scanning a vertical synchronous signal terminal, a horizontal/composite synchronous signal terminal and a synchronous-on-green terminal of the computer system. In accordance with the detected input forms, the vertical and horizontal synchronous signals are separated from each other and then adjusted in polarity. Therefore, the present invention requires no separate hardware for the separation and polarity adjustment of the vertical and horizontal synchronous signals, resulting in simplification in circuit construction and reductions in number of used components and size of a printed circuit board.

摘要翻译： 一种用于从计算机系统检测和分离垂直和水平同步信号的方法。 通过扫描计算机系统的垂直同步信号端子，水平/复合同步信号端子和同步绿色端子来检测来自计算机系统的垂直和水平同步信号的输入形式。 根据检测到的输入形式，垂直和水平同步信号彼此分离，然后在极性上进行调整。 因此，本发明不需要用于垂直和水平同步信号的分离和极性调整的单独的硬件，导致电路结构的简化和使用的部件的数量的减少以及印刷电路板的尺寸的减少。

公开(公告)号：US07253844B2

公开(公告)日：2007-08-07

申请号：US09952320

申请日：2001-09-10

申请人： Reino J. Hiltunen ,  Raimo Santahuhta

发明人： Reino J. Hiltunen ,  Raimo Santahuhta

IPC分类号： H04N5/06 ,  H04N5/08 ,  H04N5/10 ,  H04N5/50 ,  H04N5/445 ,  H04N9/45 ,  H04N9/455 ,  H03L7/00

CPC分类号： H04N5/4401 ,  H04N5/44504 ,  H04N5/46 ,  H04N21/42638 ,  H04N21/4307

摘要： A method and an arrangement are disclosed for synchronizing on-screen display functions during analog signal reception in a terminal arrangement that is capable of receiving both digital and analog video signals. There are provided means (312, 313) for generating on-screen display objects. Coupled to said means for generating on-screen display objects, there are synchronization pulse generation means (314) for controlling the generation of on-screen display objects. Comparison means (322) are used for comparing synchronization pulses generated by said synchronization pulse generation means (314) with a synchronization signal obtained (320) from an analog video signal. The result of said comparing as a controlling signal is conveyed (323, 324) to a process (314, 325) of generating said synchronization pulses.

摘要翻译： 公开了一种用于在能够接收数字和模拟视频信号的终端装置中的模拟信号接收期间同步屏幕显示功能的方法和装置。 提供了用于产生屏上显示对象的装置（312,313）。 耦合到所述用于产生屏幕显示对象的装置，存在用于控制屏幕显示对象的生成的同步脉冲产生装置（314）。 比较装置（322）用于将由所述同步脉冲发生装置（314）生成的同步脉冲与从模拟视频信号获得的同步信号（320）进行比较。 作为控制信号的所述比较的结果被传送到产生所述同步脉冲的处理（314,325）（323,324）。

公开(公告)号：US07218737B1

公开(公告)日：2007-05-15

申请号：US10224995

申请日：2002-08-21

申请人： James D. Lyle

发明人： James D. Lyle

IPC分类号： H04N5/10 ,  H04N5/08 ,  H04N5/935 ,  H04N5/92

CPC分类号： H04N21/4408 ,  G09G5/006 ,  G09G2370/047 ,  H04N5/935 ,  H04N7/1675 ,  H04N21/4122 ,  H04N21/4367 ,  H04N21/4405

摘要： A method for adaptively filtering a control signal in a serial link includes monitoring for a blanking interval in a video stream having an associated clock signal and monitoring for an occurrence of a VSYNC signal once the blanking interval has started. A control signal is initially detected wherein the control signal occurs subsequent to the occurrence of the VSYNC signal. A set of properties of the control signal are recorded and a set of filter parameters are adjusted for detecting the control signal in a next blanking period based on the set of properties of the control signal.

摘要翻译： 一种用于对串行链路中的控制信号进行自适应滤波的方法包括监视具有相关时钟信号的视频流中的消隐间隔，并且一旦消隐间隔开始就监视V SYNC信号的出现 。 最初检测到控制信号，其中控制信号在V SYNC信号发生之后发生。 记录控制信号的一组属性，并且调整一组滤波器参数，以便基于控制信号的属性集在下一个消隐周期中检测控制信号。

公开(公告)号：US07050111B2

公开(公告)日：2006-05-23

申请号：US10280737

申请日：2002-10-25

申请人： Diego Coste

发明人： Diego Coste

IPC分类号： H04N5/10

CPC分类号： H04N5/10 ,  H04N5/126

摘要： A synchronization process may include detecting successive horizontal synchronization pulses of a video signal, and a phase comparison between the successive detected pulses and the successive transitions of the reference signal for controlling the oscillator of the phase-locked loop. The detection of each horizontal synchronization pulse may include sampling the video signal, low-pass filtering the sampled signal, thresholding the filtered signal for leaving pulses having a level below a threshold. The synchronization process may also include selecting, as a function of predetermined selection criteria, from among the residual pulses within an observation window centered on a transition of the reference signal for the one which corresponds to the horizontal synchronization pulse.

公开(公告)号：US20050225676A1

公开(公告)日：2005-10-13

申请号：US10518828

申请日：2003-06-23

申请人： Philippe Belin ,  Nicolas Guillerm

发明人： Philippe Belin ,  Nicolas Guillerm

IPC分类号： H04N5/08 ,  H04N5/10 ,  H04N9/455

CPC分类号： H04N5/10

摘要： The invention relates a method of extracting synchronization signals from an input video signal (Csync) comprising horizontal synchronization pulses at the start of video lines, for generating a horizontal synchronization signal (Hsync), said method comprising:—a calculation step (105) for calculating the duration (D) of the video lines in said input video signal (Csync),—a forcing step (108) for forcing said input video signal (Csync) to an output level, said output level corresponding to the level of said input video signal (Csync) after the horizontal synchronization pulses, said input signal (Csync) being forced between the end of each horizontal synchronization pulse and a moment defined by a first percentage (X1) of said line duration (D), for generating said horizontal synchronization signal (Hsync). Use: Extraction of synchronization signals.

摘要翻译： 本发明涉及一种从视频行开始处包括水平同步脉冲的输入视频信号（Csync）提取同步信号的方法，用于产生水平同步信号（Hsync），所述方法包括： - 计算步骤（105），用于 计算所述输入视频信号（Csync）中的视频行的持续时间（D）， - 强制步骤（108），用于将所述输入视频信号（Csync）强制为输出电平，所述输出电平对应于所述输入的电平 视频信号（Csync），所述输入信号（Csync）被强制在每个水平同步脉冲的结束和由所述线路持续时间（D）的第一百分比（X 1）定义的力矩之间，用于产生所述 水平同步信号（Hsync）。 使用：提取同步信号。

公开(公告)号：US06870569B1

公开(公告)日：2005-03-22

申请号：US09906433

申请日：2001-07-16

申请人： Peyman Hojabri

发明人： Peyman Hojabri

IPC分类号： H04N5/10 ,  H04N5/18 ,  H04N11/04 ,  H03H11/26

CPC分类号： H04N5/10 ,  H04N5/18

摘要： An integrated circuit with a signal demultiplexor for separating out two signals of different magnitudes from within a multiplexed signal without requiring a large capacitance for signal filtering. A multiple-threshold input comparator stage separates the multiplexed input signal into a first fully demultiplexed signal and a first partially demultiplexed signal. The first fully and partially demultiplexed signals are logically processed in an Exclusive-OR gate to produce a second partially demultiplexed signal which is then time-delayed and gated by the first fully demultiplexed signal. The resultant gated signal is low pass filtered to produce a second fully demultiplexed signal. In a video signal application, the multiplexed input signal would be a “sandcastle” signal containing both horizontal clamp and vertical synchronization signals, with the horizontal clamp signal component being greater in magnitude than the vertical synchronization signal component, and the resulting first and second fully demultiplexed signals would be the separated horizontal clamp and vertical synchronization signals, respectively.

摘要翻译： 一种具有信号解复用器的集成电路，用于从多路复用信号中分离不同幅度的两个信号，而不需要用于信号滤波的大电容。 多阈值输入比较器级将多路复用输入信号分离为第一完全解复用信号和第一部分解复用信号。 第一个完全和部分解复用的信号在异或门逻辑处理以产生第二部分解复用的信号，然后由第一完全解复用的信号被时间延迟和门控。 所得的门控信号被低通滤波以产生第二完全解复用的信号。 在视频信号应用中，复用的输入信号将是包含水平钳位和垂直同步信号的“沙堡”信号，水平钳位信号分量的幅度大于垂直同步信号分量，并且所得到的第一和第二完全 解复用的信号分别是分离的水平钳位和垂直同步信号。

公开(公告)号：US06864884B2

公开(公告)日：2005-03-08

申请号：US09906785

申请日：2001-07-18

申请人： Toshihisa Nakano ,  Akihiko Inoue ,  Yuji Sato ,  Tomoyuki Ishihara

发明人： Toshihisa Nakano ,  Akihiko Inoue ,  Yuji Sato ,  Tomoyuki Ishihara

IPC分类号： H04N5/04 ,  G09G3/20 ,  G09G5/00 ,  G09G5/12 ,  G09G5/18 ,  H04N5/06 ,  H04N5/10

CPC分类号： H04N5/06 ,  G09G5/006 ,  G09G5/12 ,  H04N5/10

摘要： A synchronization signal generation circuit includes: a synchronization signal generation section for generating a first vertical synchronization signal and a first horizontal synchronization signal based on an externally-supplied second vertical synchronization signal; and a detection section for detecting the second vertical synchronization signal, wherein when the second vertical synchronization signal is detected by the detection section for the first time, the first vertical synchronization signal is not output by the synchronization signal generation section, and when the second vertical synchronization signal is detected by the detection section for the next time at a predetermined timing, the first vertical synchronization signal is output by the synchronization signal generation section.

摘要翻译： 同步信号产生电路包括：同步信号产生部分，用于根据外部提供的第二垂直同步信号产生第一垂直同步信号和第一水平同步信号; 以及检测部分，用于检测第二垂直同步信号，其中当第一次由检测部分检测到第二垂直同步信号时，第一垂直同步信号不由同步信号产生部分输出，并且当第二垂直同步信号 同步信号由检测部分在预定定时下次检测，第一垂直同步信号由同步信号产生部分输出。