摘要:
Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.
摘要:
The disclosure relates to a method and apparatus for detecting and blocking unauthorized MAC addresses used by virtual machines. In one embodiment, the disclosure provides automated and consistent verification of VM traffic against values assigned to each VM by network administrator. In another embodiment, the disclosure provides for validating a newly discovered VM by comparing its attributes with the corresponding description of the known VMs stored at a database. A re-validation check may also be implemented. If the VM is validated, the VM will be processed according to network policy to support features including VMReady. If the VM fails validation, other actions can be taken.
摘要:
An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.
摘要:
A plasma processing system includes a processing chamber, a substrate holder configured to hold a substrate for plasma processing, and a gas injection assembly. The gas injection assembly includes a first evacuation port located substantially in a center of the gas injection assembly and configured to evacuate gases from a central region of the substrate, and a gas injection system configured to inject gases in the process chamber. The plasma processing system also includes a second evacuation port configured to evacuate gases from a peripheral region surrounding the central region of the substrate.
摘要:
Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.
摘要:
Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.
摘要:
A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.
摘要翻译:用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。 我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。 我们提供与NFET栅极相邻的NFET SDE区域,并提供与PFET栅极相邻的PFET SDE区域。 我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。 我们在凹槽中形成PFET嵌入式源极/漏极应力器。 我们在NFET SDE区域上形成NFET S / D外延Si层,并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。 在随后的自对准硅化物步骤中,在PFET嵌入式源极/漏极应力源上的外延Si层被消耗,以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。 我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入,以形成升高的NFET源极/漏极。
摘要:
Disclosed are embodiments that provide near real-time monitoring of a control application in a manufacturing environment to detect and determine the root cause of faults within the control application. The embodiments monitor the flow of data within the control application during events (i.e., transactions, stages, process steps, etc.). By comparing a dataflow path for a near real-time event with historical dataflow path records, dataflow interruptions (i.e., fails) within the control application can be detected. By determining the location of such a dataflow interruption, the root cause of the control application fail can be determined. Additionally, the invention can generate summary reports indicating the status of the control application. For example, the summary reports can quantify the performance and/or the effectiveness of the control application. These summary reports can further be generated with drill downs to provide a user with direct access to the records upon which the reports were based.
摘要:
A method of generating a fingerprint of a bit sequence includes determining a relative occurrence frequency of each bit combination of a set of bit combinations in the bit sequence, wherein the set of bit combinations comprises all possible non-redundant sub-sequences of bits having at least one bit and at most a preset maximal number of bits. The method further includes determining for each bit combination of the set of bit combinations a difference value between the relative occurrence frequency of the bit combination and a random occurrence frequency, the random occurrence frequency relating to the expected random occurrence of the bit combination in the bit sequence. Moreover, the method includes allocating a set of bins, each bin of the set of bins being associated with a predetermined interval of difference values, each bin further relating to a bin value. The difference value of each bit combination is assigned to the bin which is associated with the interval of difference values in which the difference value of the corresponding bit combination lies. A fingerprint of the bit sequence is generated by use of the bin values of the bins to which a difference value has been assigned.
摘要:
A system is provided which utilizes a threading service to offer enhanced features for a document management system including an email system. Various enhanced email features may be provided through one or more of the following components: a delete module, a reply module, a profile module, and a search module. The delete module enables a user to delete a selected message, a set of related messages, or the whole set except for the selected message. The reply module enables a user to send a reply message to all addresses associated and involved with an entire set of related messages. The profile module enables a dynamic interest profile to contain all relevant information from an outgoing message and a set of messages related to the outgoing message. The search module enables search results to include documents which match the user's query as well as documents related to the documents which match the user's query.