公开(公告)号：US5774100A

公开(公告)日：1998-06-30

申请号：US721620

申请日：1996-09-26

申请人： Yoshiro Aoki ,  Youichi Masuda

发明人： Yoshiro Aoki ,  Youichi Masuda

IPC分类号： G09G3/00 ,  G09G3/36

CPC分类号： G09G3/006 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2330/10 ,  G09G2330/12 ,  Y10S345/904

摘要： An array substrate of an LCD device includes a glass substrate, an n.times.m number of pixel electrodes arrayed in a matrix form on the glass substrate, an n-number of scanning lines formed along rows of the pixel electrodes on the glass substrate, an m-number of signal lines formed along columns of the pixel electrodes on the glass substrate, switching elements formed on the glass substrate and located adjacent to intersections of the scanning lines and signal lines, each switching element supplying a video signal from the signal line to the pixel electrode in response to a scanning signal supplied from the scanning line, and a test supporting circuit for sensing potentials of the scanning lines. The test supporting circuit includes a test section comprising an n-number of testing thin film transistors whose gates are connected to the scanning lines and a test wiring section connected to source-drain paths of the testing thin film transistors thereby to detect the operation states of the testing thin film transistors corresponding to the gate potentials thereof. The test wiring section includes first and second test pads between which the source-drain paths of the testing thin film transistors are connected in parallel, a third test pad to which a test voltage is applied with the first test pad used as a reference, and a resistive element connected between the second and third test pads, the test voltage being divided according to a resistance ratio between the resistive element and the testing thin film transistors.

摘要翻译： LCD装置的阵列基板包括玻璃基板，在玻璃基板上排列成矩阵形式的n×m个像素电极，沿着玻璃基板上的像素电极列排列的n条扫描线， 沿着玻璃基板上的像素电极的列形成的信号线的数量，形成在玻璃基板上并且位于扫描线和信号线的交叉点附近的开关元件，每个开关元件从信号线向像素提供视频信号 响应于从扫描线提供的扫描信号的电极和用于感测扫描线的电位的测试支持电路。 测试支持电路包括测试部分，其包括n个测试薄膜晶体管，其栅极连接到扫描线，以及连接到测试薄膜晶体管的源极 - 漏极路径的测试布线部分，从而检测其中的操作状态 测试薄膜晶体管对应于其栅极电位。 测试布线部分包括测试薄膜晶体管的源极 - 漏极路径并联连接的第一和第二测试焊盘，第一测试焊盘用作参考的施加测试电压的第三测试焊盘，以及 连接在第二和第三测试焊盘之间的电阻元件，测试电压根据电阻元件和测试薄膜晶体管之间的电阻比进行分压。

公开(公告)号：US5356830A

公开(公告)日：1994-10-18

申请号：US627922

申请日：1990-12-17

申请人： Susumu Yoshikawa ,  Shuichi Samata ,  Satoshi Maeda ,  Shizuo Sawada

发明人： Susumu Yoshikawa ,  Shuichi Samata ,  Satoshi Maeda ,  Shizuo Sawada

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L29/43

CPC分类号： H01L21/28525 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76879

摘要： A semiconductor device and its manufacturing method are provided in which an epitaxial silicon layer is formed by a selective epitaxial growth method over a semiconductor substrate and a polysilicon layer is formed by an ordinary deposition method on the epitaxial silicon layer and these layers and are formed over a semiconductor device in a continuous process within the same furnace for a CVD apparatus.

摘要翻译： 提供一种半导体器件及其制造方法，其中在半导体衬底上通过选择性外延生长方法形成外延硅层，并且通过普通沉积方法在外延硅层和这些层上形成多晶硅层 在用于CVD设备的同一炉内的连续工艺中的半导体器件。

公开(公告)号：US5760425A

公开(公告)日：1998-06-02

申请号：US790457

申请日：1997-01-29

申请人： Ikuko Kobayashi ,  Michiaki Hiyoshi

发明人： Ikuko Kobayashi ,  Michiaki Hiyoshi

IPC分类号： H01L25/11 ,  H01L21/52 ,  H01L23/043 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L23/043 ,  H01L24/01

摘要： The top-side (n-type) electrode and bottom-side (p-type) electrode of a Si chip with a p-n junction are pressed against a Cu cathode electrode and a Cu anode electrode via Mo plates respectively, thereby establishing electrical connection. The inner wall of a case is round and the Si chip is almost square. The top of the case is covered with ceramic, for example. A washer is a compression member. A chip frame holds the Si chip and Mo plates in compression positions and simultaneously determines their locations within the case. Specifically, the side face of the Si chip is not flush with the side face of each of the Mo plates. This enables the chip frame to make the creepage distance longer. Since the chip frame is a single chip frame without any joint, the creepage distance between the anode and cathode electrodes is defined by part of the chip frame that faces part of the surface of the Si chip and parts of the surfaces of the Mo plates sandwiching the Si chip between them.

摘要翻译： 具有p-n结的Si芯片的顶侧（n型）电极和底侧（p型）电极分别通过Mo板压在Cu阴极电极和Cu阳极上，从而建立电连接。 外壳的内壁是圆形的，Si芯片几乎是正方形的。 例如，顶部覆盖着陶瓷。 垫圈是压缩构件。 芯片框架将Si芯片和Mo板保持在压缩位置，同时确定其在壳体内的位置。 具体地说，Si芯片的侧面不与每个Mo板的侧面齐平。 这使得芯片框架能够使爬电距离更长。 由于芯片框架是没有任何接头的单个芯片框架，所以阳极和阴极电极之间的爬电距离由芯片框架的一部分限定，该部分芯片框架面向Si芯片表面的一部分，Mo板的部分表面夹持 他们之间的Si芯片。

公开(公告)号：US08823376B2

公开(公告)日：2014-09-02

申请号：US13683587

申请日：2012-11-21

申请人： Kabushiki Kaisha Toshiba ,  Toshiba Medical Systems Corporation

发明人： Yuichi Yamashita ,  Nobuyasu Ichinose ,  Shinichi Kitane

IPC分类号： G01V3/00 ,  A61B5/055

CPC分类号： G01R33/28 ,  A61B5/0042 ,  A61B5/055 ,  A61B5/7285 ,  G01R33/54 ,  G01R33/5602 ,  G01R33/56333 ,  G06T7/0012

摘要： A magnetic resonance imaging apparatus includes a magnetic resonance data acquisition unit and a cerebrospinal fluid image data generation unit. The magnetic resonance data acquisition unit consecutively acquires a plurality of magnetic resonance data for generating a plurality of cerebrospinal fluid image data, each corresponding to a different data acquisition time, after a labeling pulse is applied. The cerebrospinal fluid image data generation unit generates the plurality of cerebrospinal fluid image data based on the plurality of magnetic resonance data.

摘要翻译： 磁共振成像装置包括磁共振数据获取单元和脑脊液图像数据生成单元。 在施加标记脉冲之后，磁共振数据获取单元连续地获取用于产生多个脑脊液图像数据的多个磁共振数据，每个脑脊液图像数据对应于不同的数据获取时间。 脑脊液图像数据生成单元基于多个磁共振数据生成多个脑脊液图像数据。

公开(公告)号：US5293334A

公开(公告)日：1994-03-08

申请号：US799078

申请日：1991-11-27

申请人： Mitsuru Shimizu

发明人： Mitsuru Shimizu

IPC分类号： H01L21/822 ,  G11C5/14 ,  G11C11/401 ,  H01L27/04 ,  H01L27/10

CPC分类号： G11C5/14

摘要： A first power source line is formed around a memory area having a memory cell array, column decoder, row decoder and sense amplifier formed therein. The first power source line is applied with a potential which is obtained by lowering a power source voltage supplied from the exterior. A second power source line is formed in the surrounding region of the first power source line. The second power source line is applied with a ground potential. A first peripheral circuit driven by a voltage between the lowered potential and the ground potential is disposed in an area between the first and second power source lines. The first peripheral circuit is a circuit used for the memory area. A third power source line is formed in the surrounding region of the second power source line. The third power source line is applied with a power source potential supplied from the exterior. A second peripheral circuit driven by a voltage between the power source potential and the ground potential is disposed in an area between the second and third power source lines. The second peripheral circuit is a circuit used for an external circuit of a chip.

摘要翻译： 在具有形成在其中的存储单元阵列，列解码器，行解码器和读出放大器的存储区域周围形成第一电源线。 第一电源线被施加有通过降低从外部供应的电源电压而获得的电位。 第二电源线形成在第一电源线的周围区域。 第二电源线被施加接地电位。 由第一和第二电源线之间的区域设置由降低电位和接地电位之间的电压驱动的第一外围电路。 第一外围电路是用于存储区域的电路。 第三电源线形成在第二电源线的周围区域。 第三电源线施加有从外部供应的电源电位。 由电源电位和地电位之间的电压驱动的第二外围电路设置在第二和第三电源线之间的区域中。 第二外围电路是用于芯片的外部电路的电路。