公开(公告)号：US5356830A

公开(公告)日：1994-10-18

申请号：US627922

申请日：1990-12-17

申请人： Susumu Yoshikawa ,  Shuichi Samata ,  Satoshi Maeda ,  Shizuo Sawada

发明人： Susumu Yoshikawa ,  Shuichi Samata ,  Satoshi Maeda ,  Shizuo Sawada

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L29/43

CPC分类号： H01L21/28525 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76879

摘要： A semiconductor device and its manufacturing method are provided in which an epitaxial silicon layer is formed by a selective epitaxial growth method over a semiconductor substrate and a polysilicon layer is formed by an ordinary deposition method on the epitaxial silicon layer and these layers and are formed over a semiconductor device in a continuous process within the same furnace for a CVD apparatus.

摘要翻译： 提供一种半导体器件及其制造方法，其中在半导体衬底上通过选择性外延生长方法形成外延硅层，并且通过普通沉积方法在外延硅层和这些层上形成多晶硅层 在用于CVD设备的同一炉内的连续工艺中的半导体器件。

公开(公告)号：US5187566A

公开(公告)日：1993-02-16

申请号：US646496

申请日：1991-01-28

申请人： Susumu Yoshikawa ,  Junpei Kumagai ,  Shizuo Sawada ,  Yasuo Matsumoto

发明人： Susumu Yoshikawa ,  Junpei Kumagai ,  Shizuo Sawada ,  Yasuo Matsumoto

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10829 ,  H01L27/10835

摘要： In a semiconductor memory of the invention, the source or drain of a transfer gate MOS transistor is electrically connected to a charge storage first conductive layer through a third conductive layer.

摘要翻译： 在本发明的半导体存储器中，传输门MOS晶体管的源极或漏极通过第三导电层电连接到电荷存储第一导电层。

公开(公告)号：US4916521A

公开(公告)日：1990-04-10

申请号：US223971

申请日：1988-07-25

申请人： Susumu Yoshikawa ,  Shizuo Sawada

发明人： Susumu Yoshikawa ,  Shizuo Sawada

IPC分类号： H01L21/768 ,  H01L23/485

CPC分类号： H01L23/485 ,  H01L2924/0002

摘要： A first insulation layer is formed on a semiconductor substrate, and a first conductive layer is formed on the first insulation layer. A second insulation layer is formed on the first conductive layer and the first insulation layer, and a first contact hole, having a width greater than that of the first conductive layer, is formed in the second insulation layer, at a position corresponding to the first conductive layer. A second conductive layer, having a width greater than that of the first contact hole, is formed on the second insulation layer and in the first contact hole, and is formed in contact with the upper and side surfaces of the first conductive layer located inside the second contact hole. A third insulation layer is formed on the second conductive layer and the second insulation layer, and a second contact hole, having a width less than that of the second conductive layer, is formed in the third insulation layer, at a position corresponding to the second conductive layer. A third conductive layer, having a width greater than that of the second contact hole but less than that of the second conductive layer, is formed on the third conductive layer and in the second contact hole. The first conductive layer is electrically connected to the third conductive layer.

摘要翻译： 在半导体衬底上形成第一绝缘层，在第一绝缘层上形成第一导电层。 第二绝缘层形成在第一导电层和第一绝缘层上，并且具有大于第一导电层的宽度的第一接触孔形成在第二绝缘层中的与第一绝缘层相对应的位置处的第一绝缘层 导电层。 在第二绝缘层和第一接触孔中形成具有大于第一接触孔的宽度的第二导电层，并且形成为与位于第一接触孔内部的第一导电层的上表面和侧表面接触 第二接触孔。 在第二绝缘层上形成第三绝缘层，第二绝缘层和宽度小于第二导电层宽度的第二接触孔形成在第三绝缘层中，对应于第二绝缘层的第二绝缘层 导电层。 在第三导电层和第二接触孔中形成具有大于第二接触孔的宽度但小于第二导电层的宽度的第三导电层。 第一导电层电连接到第三导电层。

公开(公告)号：US5110766A

公开(公告)日：1992-05-05

申请号：US549632

申请日：1990-07-06

申请人： Satoshi Maeda ,  Shizuo Sawada ,  Satoshi Shinozaki

发明人： Satoshi Maeda ,  Shizuo Sawada ,  Satoshi Shinozaki

IPC分类号： H01L21/768 ,  H01L27/108

CPC分类号： H01L21/76819 ,  H01L21/76877 ,  H01L27/10805

摘要： A method of manufacturing a semiconductor device, in particular a contact portion of the wiring of the device. An insulating layer is formed on a semiconductor substrate, a contact hole is formed on the insulating layer by etching, and a first conductive layer having hollows is formed on the insulating layer and in the contact hole. Next, a flattening layer is formed to flatten the surface of device structure, and a part of the first conductive layer is exposed by etching the flattening layer to permit a part of the flattening layer to remain in hollows of device structure. Next, a second conductive layer is formed on the remaining flattening layer and the exposed part of the first conductive layer, and is connected to the semiconductor substrate.

公开(公告)号：US4833647A

公开(公告)日：1989-05-23

申请号：US903997

申请日：1986-09-05

申请人： Satoshi Maeda ,  Shizuo Sawada

发明人： Satoshi Maeda ,  Shizuo Sawada

IPC分类号： H01L27/10 ,  G11C11/34 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/10805

摘要： The semiconductor memory device of the present invention is formed on an integrated substrate and is immune to alpha radiation. The device includes a semiconductor substrate of a first conductive type and a memory cell formed in the substrate which has a switching MOS transistor having at least a first impurity region of a second conductive type and a capacitor connected to the transistor for storing memory data. A second impurity region of the first conductive type and having a higher concentration than that of the substrate is provided on the substrate surface at a position covering the first impurity region.

摘要翻译： 本发明的半导体存储器件形成在集成的衬底上并且不受α辐射的影响。 该器件包括第一导电类型的半导体衬底和形成在衬底中的存储单元，该存储单元具有至少具有第二导电类型的第一杂质区域的开关MOS晶体管和连接到用于存储存储器数据的晶体管的电容器。 在覆盖第一杂质区域的位置处，在基板表面上设置第一导电类型的第二杂质区域并且具有比基板更高的浓度。

公开(公告)号：US5004704A

公开(公告)日：1991-04-02

申请号：US428903

申请日：1989-10-30

申请人： Satoshi Maeda ,  Shizuo Sawada

发明人： Satoshi Maeda ,  Shizuo Sawada

IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76837 ,  H01L21/31051 ,  H01L21/76834 ,  Y10S148/133

摘要： A Phospho Silicate Glass layer is used for an insulation layer between a lower wiring layer including a refractory metal silicide and an upper wiring layer in a semiconductor device of a multilevel interconnection structure. A reflow treatment is performed on the Phospho Silicate Glass layer using steam. A part of the lower wiring layer is oxidized during the reflow treatment, and the resistivity of the lower wiring layer is simultaneously lowered during the reflow treatment.

公开(公告)号：US4410375A

公开(公告)日：1983-10-18

申请号：US307875

申请日：1981-10-02

申请人： Shizuo Sawada ,  Hiroshi Iwai ,  Satoshi Maeda

发明人： Shizuo Sawada ,  Hiroshi Iwai ,  Satoshi Maeda

IPC分类号： H01L27/10 ,  H01L21/225 ,  H01L21/3105 ,  H01L21/322 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/2255 ,  H01L21/3105 ,  H01L27/10805

摘要： A method for fabricating a semiconductor device is disclosed which includes a step of forming contact holes in insulating films on a substrate, forming a silicate glass layer containing an impurity over the entire surface, and performing the phosphorus getter treatment using POCl.sub.3 at a high temperature. Even when the phosphorus getter treatment is performed after the formation of the contact holes, the substrate or electrodes exposed through the contact holes may not be reduced in thickness or damaged. The impurity may be diffused into the substrate from the silicate glass layer through the contact holes.

摘要翻译： 公开了一种制造半导体器件的方法，其包括在基片上形成绝缘膜中的接触孔的步骤，在整个表面上形成含有杂质的硅酸盐玻璃层，并在高温下使用POCl 3进行磷吸气剂处理。 即使在形成接触孔之后进行磷吸气剂处理，也可能不会使通过接触孔露出的基板或电极的厚度减小或损坏。 杂质可以从硅酸盐玻璃层通过接触孔扩散到衬底中。

公开(公告)号：US4951175A

公开(公告)日：1990-08-21

申请号：US353765

申请日：1989-05-18

申请人： Kei Kurosawa ,  Hidehiro Watanabe ,  Shizuo Sawada

发明人： Kei Kurosawa ,  Hidehiro Watanabe ,  Shizuo Sawada

IPC分类号： H01L27/108

CPC分类号： H01L27/10808 ,  H01L27/10835

摘要： A dynamic random access memory with a stacked capacitor cell structure is disclosed which has a memory cell provided on a silicon substrate and having a MOSFET and a capacitor. An insulative layer is formed on the substrate, and a first polycrystalline silicon layer is formed on this insulative layer. These layers are simultaneously subjected to etching and define a contact hole which penetrates them to come in contact with the surface of the source. A second polycrystalline silicon layer is formed on the first polycrystalline silicon layer to uniformly cover the inner wall of the contact hole and that surface portion of the source which is exposed through the contact hole. The first and second silicon layers are simultaneously subjected to patterning to provide the lower electrode of the capacitor. After a capacitor insulation layer is formed on the second polycrystalline silicon layer, a third polycrystalline silicon layer is formed on the capacitor insulation layer so as to bury a recess of the second polycrystalline silicon layer. The third silicon layer constitutes the upper electrode of the capacitor.

摘要翻译： 公开了一种具有层叠电容器单元结构的动态随机存取存储器，其具有设置在硅衬底上并具有MOSFET和电容器的存储单元。 在基板上形成绝缘层，在该绝缘层上形成第一多晶硅层。 这些层同时进行蚀刻并限定穿透它们的接触孔以与源的表面接触。 在第一多晶硅层上形成第二多晶硅层，以均匀地覆盖接触孔的内壁和通过接触孔露出的源的表面部分。 第一和第二硅层同时进行图案化以提供电容器的下电极。 在第二多晶硅层上形成电容器绝缘层之后，在电容器绝缘层上形成第三多晶硅层，从而埋入第二多晶硅层的凹部。 第三硅层构成电容器的上电极。

公开(公告)号：US07023044B2

公开(公告)日：2006-04-04

申请号：US10893914

申请日：2004-07-20

申请人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

发明人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

公开(公告)号：US06846733B2

公开(公告)日：2005-01-25

申请号：US10388462

申请日：2003-03-17

申请人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

发明人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

摘要翻译： 第一和第二布线形成在第一绝缘膜上。 每个布线被布置成使得导电膜，氧化硅膜和氮化硅膜层压。 此后，在整个表面上形成氧化硅绝缘膜。 蚀刻氧化硅绝缘膜，使得在第一和第二布线之间形成接触孔。 由于在每个布线的导电膜上存在氧化硅膜和氮化硅膜，因此在蚀刻时导电膜不会露出。 此后，在接触孔的侧壁上形成绝缘膜，并且通过接触孔露出的导电膜被绝缘膜覆盖。