公开(公告)号：US5327381A

公开(公告)日：1994-07-05

申请号：US892919

申请日：1992-06-03

申请人： Larry D. Johnson ,  Mark G. Johnson

发明人： Larry D. Johnson ,  Mark G. Johnson

IPC分类号： G11C8/10 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/84 ,  G11C8/10

摘要： A fused decoder for selecting one or more elements of an array, such as a row of memory, is provided. The corresponding row of memory can be permanently deselected by blowing the fuse of the decoder. Array components such as a redundant row of memory, can be substituted for the deselected component. The decoder includes a gate formed exclusively from NMOS transistors so that the decoder can provide a select signal in response to an address without an PMOS transistor responding to the address- By eliminating PMOS transistors from the gate portion of the decoder, the load presented to the address lines is reduced.

摘要翻译： 提供了用于选择阵列的一个或多个元件（例如存储器行）的融合解码器。 通过吹送解码器的熔丝可以永久取消相应的存储器行。 诸如冗余行存储器的阵列组件可以替代被取消选择的组件。 解码器包括仅由NMOS晶体管形成的栅极，使得解码器可以响应于没有PMOS晶体管响应于地址而提供选择信号。通过从解码器的栅极部分消除PMOS晶体管，呈现给 地址线减少。

公开(公告)号：US4953073A

公开(公告)日：1990-08-28

申请号：US827269

申请日：1986-02-06

申请人： John P. Moussouris ,  Lester M. Crudele ,  Steven A. Przybylski

发明人： John P. Moussouris ,  Lester M. Crudele ,  Steven A. Przybylski

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0848 ,  G06F12/1054

摘要： A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses.

摘要翻译： 基于缓存的计算机体系结构具有将地址生成单元和标签比较器封装在一起并与高速缓存RAMS分离。 如果架构支持虚拟存储器，地址转换单元可以包括在与地址生成单元和标签比较器逻辑之间的逻辑上相同的芯片上。 此外，可以在外部地址，数据和标签总线上实现对多于一个高速缓存的交织访问。

公开(公告)号：US5386562A

公开(公告)日：1995-01-31

申请号：US882427

申请日：1992-05-13

申请人： Suneel Jain ,  Frederick Chow ,  Sun Chan ,  Sin S. Lew

发明人： Suneel Jain ,  Frederick Chow ,  Sun Chan ,  Sin S. Lew

IPC分类号： G06F9/45 ,  G06F9/30 ,  G06F9/00

CPC分类号： G06F8/452

摘要： A procedure which is a particular type of software pipelining is provided which increases the efficiency with which code is executed by reducing or eliminating stalls such as by filling delay slots. The process includes moving instructions in a loop from one loop iteration to another. The moving of instructions provides the scheduler with additional independent instructions in a given basic block so the scheduler has greater freedom to move instructions into unfilled delay slots. The procedure includes changing the entry point into the loop, thus effectively moving an instruction from near the top of the loop to near the bottom of the loop, while changing the iteration number of the moved instruction.

摘要翻译： 提供了作为特定类型的软件流水线化的过程，其通过减少或消除诸如通过填充延迟时隙的失速来提高代码执行的效率。 该过程包括将循环中的指令从一个循环迭代移动到另一个循环迭代。 指令的移动向调度器提供给定基本块中的附加独立指令，因此调度器具有将指令移动到未填充延迟时隙的更大自由度。 该过程包括将入口点更改为循环，从而有效地将指令从循环顶部附近移动到靠近循环底部，同时改变移动指令的迭代次数。

公开(公告)号：US5113506A

公开(公告)日：1992-05-12

申请号：US491114

申请日：1990-03-09

申请人： John P. Moussouris ,  Lester M. Crudele ,  Steven A. Przybylski

发明人： John P. Moussouris ,  Lester M. Crudele ,  Steven A. Przybylski

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0848 ,  G06F12/1054

摘要： A cache-based computer architecture is disclosed in which the address generating unit and the tag comparator are packaged together and separately from the cache RAMs. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and the tag busses.

摘要翻译： 公开了一种基于缓存的计算机架构，其中地址生成单元和标签比较器被封装在一起并与高速缓冲存储器RAM分开。 如果架构支持虚拟存储器，地址转换单元可以包括在与地址生成单元和标签比较器逻辑之间的逻辑上相同的芯片上。 此外，可以在外部地址，数据和标签总线上实现对多于一个高速缓存的交织访问。

公开(公告)号：US5027270A

公开(公告)日：1991-06-25

申请号：US255791

申请日：1988-10-11

申请人： Thomas J. Riordan ,  Paul S. Ries ,  Edwin L. Hudson ,  Earl A. Killian

发明人： Thomas J. Riordan ,  Paul S. Ries ,  Edwin L. Hudson ,  Earl A. Killian

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3814 ,  G06F12/0859 ,  G06F9/3802

摘要： A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.

摘要翻译： 处理器，指令高速缓存和主存储器之间的处理器控制的接口提供用于从主存储器中的指令块同时重新填充高速缓存并且在块被写入高速缓存时处理该块中的指令。

公开(公告)号：US4879676A

公开(公告)日：1989-11-07

申请号：US161543

申请日：1988-02-29

申请人： Craig C. Hansen

发明人： Craig C. Hansen

IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F7/485 ,  G06F7/487 ,  G06F7/527 ,  G06F7/53 ,  G06F7/57 ,  G06F7/76 ,  G06F9/302 ,  G06F9/38

CPC分类号： G06F7/483 ,  G06F9/30014 ,  G06F9/3836 ,  G06F9/3861 ,  G06F2207/3884 ,  G06F7/4991 ,  G06F7/49942

摘要： In data processing systems of the type operable to perform floating point computations there is provided a method, and apparatus implementing that method, for predicting, in advance of the floating point computation, whether or not the computation will produce a floating point exception (e.g., overflow, underflow, etc.). The prediction method includes the steps of combining the exponent fields of the operands of the computation in a manner dictated by the type of operation (i.e., add, subtract, multiply, etc.), and comparing that combination, together with an indication of the computation to be performed (e.g., add, substract, multiply, or divide), to obtain an indication of the possibility of the computation ending in a floating point exception. If an exception is predicted, the indication can be used to halt other data processing operations until completion of the computation so that, in the event the computation actually results in a floating point exception, the handling of the exception can be accomplished with a minimum of effort.

公开(公告)号：US5297092A

公开(公告)日：1994-03-22

申请号：US892918

申请日：1992-06-03

申请人： Larry D. Johnson

发明人： Larry D. Johnson

IPC分类号： G11C7/06 ,  H03K17/16 ,  G11C11/409

CPC分类号： G11C7/065

摘要： A sense amp and latch for sensing and latching data on a plurality of bit and inverse bit lines is provided. A sense amp power line which connects the sense amp to a ground line also decouples the bit lines from the sense amp during the evaluation process. The circuit allows for automatic latching of the data which the sense amp evaluated without requiring the generation of other timing signals. Capacitive loading on each of the two sides of the sense amp are equal.

摘要翻译： 提供了用于在多个位和反向位线上检测和锁存数据的读出放大器和锁存器。 将感测放大器连接到接地线的感测放大器电源线也在评估过程中将位线与感测放大器分离。 该电路允许在不需要产生其他定时信号的情况下对感测放大器进行评估的数据进行自动锁存。 感测放大器两侧的电容负载相等。

公开(公告)号：US4805098A

公开(公告)日：1989-02-14

申请号：US860304

申请日：1986-05-05

申请人： Marvin A. Mills, Jr. ,  Lester M. Crudele

发明人： Marvin A. Mills, Jr. ,  Lester M. Crudele

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/00 ,  G06F7/00

CPC分类号： G06F13/1631

摘要： Apparatus is disclosed for buffering writes from a CPU to main memory, in which sequential write requests to the same address are gathered and combined into a single write request. The embodiment described does not permit gathering with the write request in the buffer which is next scheduled for action by the main memory bus controller, nor does it permit gathering with other than the immediately preceding write request. The invention is implemented using a plurality of buffer ranks, each comprising a data rank, an address rank, and a valid rank for indicating which bits or bytes of the data rank contain data to be written to memory.

摘要翻译： 公开了用于缓冲​​从CPU到主存储器的写入的装置，其中对相同地址的顺序写入请求被收集并组合成单个写请求。 所描述的实施例不允许在下一次由主存储器总线控制器执行动作的缓冲器中的写入请求进行采集，也不允许与紧接在前的写入请求之外的采集。 本发明使用多个缓冲器级别实现，每个缓冲器级别包括数据等级，地址级别和有效等级，用于指示数据等级的哪些位或字节包含要写入存储器的数据。

公开(公告)号：US5307477A

公开(公告)日：1994-04-26

申请号：US59715

申请日：1993-05-10

申请人： George S. Taylor ,  P. Michael Farmwald ,  Timothy P. Layman ,  Huy X. Ngo ,  Allen W. Roberts

发明人： George S. Taylor ,  P. Michael Farmwald ,  Timothy P. Layman ,  Huy X. Ngo ,  Allen W. Roberts

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0891 ,  G06F12/0888 ,  G06F12/0897 ,  G06F12/1045

摘要： A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.

摘要翻译： 一种用于包括两个主高速缓冲存储器的计算机系统的两级缓存存储器系统，一个用于存储指令，一个用于存储数据。 该系统还包括用于存储指令和数据的二级高速缓冲存储器。 主缓存和辅助缓存每个使用自己的单独的标签目录。 主缓存使用采用虚拟标签和虚拟地址的虚拟寻址方案。 二级缓存采用使用虚拟标签和部分物理地址的混合寻址方案。 主缓存和副缓存并行运行，除非较大和较慢的二级缓存正在执行先前的操作。 只有在主缓存和副缓存中遇到“未命中”，系统处理器才能访问主内存。

公开(公告)号：US5301153A

公开(公告)日：1994-04-05

申请号：US893156

申请日：1992-06-03

申请人： Larry D. Johnson

发明人： Larry D. Johnson

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/848

摘要： A redundant array element or signal line is selectively added and an defective array element or signal line is eliminated by the method and apparatus of the present invention. A multiplexor receives an input signal and a neighboring input signal and outputs one of these two input signals in response to a control signal. A fuse is provided in connection with each output line and configured such that if the fuse is unblown, the device selects the same input as was selected by its upstream neighbor. If a fuse if blown, the multiplexor will select the second input and will output a control signal to its downstream neighbor causing the downstream neighbor to also output its second input line and to output a control signal to its downstream neighbor to select the second input line. The substitution of a redundant element or line is achieved by blowing a single fuse and the circuitry adds only a single mux delay to the critical path.

摘要翻译： 选择性地添加冗余阵列元件或信号线，并且通过本发明的方法和装置消除有缺陷的阵列元件或信号线。 多路复用器接收输入信号和相邻输入信号，并响应于控制信号输出这两个输入信号中的一个。 提供与每个输出线连接的保险丝，并且被配置为使得如果保险丝未被吹出，则该设备选择与其上游邻居所选择的相同的输入。 如果熔丝熔断，则多路复用器将选择第二个输入，并向其下游邻居输出一个控制信号，导致下游邻居也输出其第二个输入线，并向其下游邻居输出一个控制信号，以选择第二条输入线 。 冗余元件或线路的替换是通过吹一个熔丝来实现的，并且该电路仅对关键路径增加单个多路延迟。