公开(公告)号：US09691756B2

公开(公告)日：2017-06-27

申请号：US13750387

申请日：2013-04-22

Applicant: Euipil Kwon

Inventor： Euipil Kwon

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/84 ,  H01L29/68 ,  H01L27/102 ,  H01L29/861 ,  H01L27/112 ,  H01L29/872 ,  H01L27/12 ,  H01L29/06 ,  G11C11/4094 ,  G11C11/4097 ,  G11C16/04

CPC classification number: H01L27/0629 ,  G11C11/4094 ,  G11C11/4097 ,  G11C16/0466 ,  G11C2207/005 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/11206 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/685 ,  H01L29/8611 ,  H01L29/872

Abstract: The nonvolatile memory device includes a memory cell having a transistor in which an insulating isolation layer is formed in a channel region. The nonvolatile memory device includes a metal-oxide-semiconductor (MOS) transistor as a basic component. An insulating isolation layer is formed in at least a channel region, and a gate insulating layer includes an insulating layer or a variable resistor and serves as a data storage. A gate includes a metal layer formed in a lower portion thereof. First source and drain regions are lightly doped with a dopant, and second source and drain regions are heavily doped with a dopant.

公开(公告)号：US09087588B2

公开(公告)日：2015-07-21

申请号：US13595426

申请日：2012-08-27

Applicant: Euipil Kwon

Inventor： Euipil Kwon

IPC: G11C17/06 ,  G11C17/18 ,  H01L27/10 ,  H01L27/102

CPC classification number: G11C17/06 ,  G11C17/18 ,  H01L27/101 ,  H01L27/1021

Abstract: A programmable non-volatile memory including a memory cell includes a transistor acting as an anti-fuse and two diodes for access. The memory cell that can store two bits and includes a transistor acting as an anti-fuse and two diodes for access, wherein the cell transistor includes: the source electrode formed by a metal; the first diode as the source region contact structure; the drain electrode formed by a metal; and the second diode as the drain region contact structure wherein the cell transistor, the oxide layer between the source area and the gate is the first anti-fuse the first storage; the oxide layer between the drain area and the gate is the second anti-fuse the second storage; the two diodes are connected in series to access the two anti-fuses.

Abstract translation: 包括存储单元的可编程非易失性存储器包括用作反熔丝的晶体管和用于存取的两个二极管。 存储单元，其可以存储两位，并且包括用作反熔丝的晶体管和用于存取的两个二极管，其中所述单元晶体管包括：由金属形成的源电极; 第一个二极管作为源区接触结构; 由金属形成的漏电极; 并且所述第二二极管作为漏区接触结构，其中所述单元晶体管，所述源极区和所述栅极之间的氧化物层是所述第一存储器的第一反熔丝; 漏极区域和栅极之间的氧化层是第二个保险丝的第二个保险丝; 两个二极管串联连接以访问两个防熔断器。

公开(公告)号：US08687408B2

公开(公告)日：2014-04-01

申请号：US13614242

申请日：2012-09-13

Applicant: Euipil Kwon

Inventor： Euipil Kwon

IPC: G11C11/00 ,  G11C5/02 ,  G11C13/00

CPC classification number: G11C5/02 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/18 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: A highly integrated programmable non-volatile memory and a manufacturing method thereof are provided. More particularly, a memory device including an antifuse and a diode, or a variable resistor and a diode, an operation method thereof, and a manufacturing method of a plurality of memory cells capable of increasing the integration density by utilizing a vertical space are provided. The highly integrated programmable non-volatile memory includes first stepped cells and second stepped cells formed to have different heights. The first stepped cells are formed on a horizontal plane with a high height, and the second stepped cells are formed on a horizontal plane with a low height.

Abstract translation: 提供了高度集成的可编程非易失性存储器及其制造方法。 更具体地，提供了包括反熔丝和二极管，或可变电阻器和二极管的存储器件，其操作方法和能够通过利用垂直空间来提高积分密度的多个存储器单元的制造方法。 高度集成的可编程非易失性存储器包括形成为具有不同高度的第一阶梯电池和第二阶梯电池。 第一台阶单元形成在高度高的水平面上，第二台阶单元形成在低高度的水平面上。