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公开(公告)号：US20230087239A1
公开(公告)日：2023-03-23
申请号：US18059812
申请日：2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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公开(公告)号：US20120139771A1
公开(公告)日：2012-06-07
申请号：US13166117
申请日：2011-06-22
Applicant: Stéphane Le Tual , Pratap Narayan Singh , Oleksiy Zabroda , Nicola Vannucci
Inventor： Stéphane Le Tual , Pratap Narayan Singh , Oleksiy Zabroda , Nicola Vannucci
IPC: H03M1/12
CPC classification number: H03M1/468
Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.
Abstract translation: 一种差分逐次逼近模数转换器，包括：比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器，所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器，所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量，其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个：第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路，其适于在采样阶段期间对差分输入电压进行采样，并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。
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公开(公告)号：US11764731B2
公开(公告)日：2023-09-19
申请号：US18059812
申请日：2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
CPC classification number: H03B5/36 , G06F1/10 , H03F3/245 , H04B1/0475 , H03B2200/004 , H03F2200/451 , H04B2001/0408
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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公开(公告)号：US11876732B2
公开(公告)日：2024-01-16
申请号：US17100505
申请日：2020-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
Inventor： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC: H04L41/0803 , H04L49/109 , G06F21/85
CPC classification number: H04L49/109 , G06F21/85 , H04L41/0803
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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公开(公告)号：US11533019B2
公开(公告)日：2022-12-20
申请号：US17180752
申请日：2021-02-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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Patent Agency Ranking
公开(公告)号：US20210265950A1
公开(公告)日：2021-08-26
申请号：US17180752
申请日：2021-02-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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公开(公告)号：US08497795B2
公开(公告)日：2013-07-30
申请号：US13166117
申请日：2011-06-22
Applicant: Stéphane Le Tual , Pratap Narayan Singh , Oleksiy Zabroda , Nicola Vannucci
Inventor： Stéphane Le Tual , Pratap Narayan Singh , Oleksiy Zabroda , Nicola Vannucci
IPC: H03M1/34
CPC classification number: H03M1/468
Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.
Abstract translation: 一种差分逐次逼近模数转换器，包括：比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器，所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器，所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量，其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个：第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路，其适于在采样阶段期间对差分输入电压进行采样，并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。
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公开(公告)号：US12068057B2
公开(公告)日：2024-08-20
申请号：US18056803
申请日：2022-11-18
Applicant: STMicroelectronics S.r.l. , STMicroelectronics International N.V. , STMicroelectronics Application GMBH
Inventor： Asif Rashid Zargar , Nicolas Bernard Grossier , Charul Jain , Roberto Colombo
CPC classification number: G11C7/24 , G11C7/1039 , G11C7/1069
Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.
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公开(公告)号：US20240213153A1
公开(公告)日：2024-06-27
申请号：US18541497
申请日：2023-12-15
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics International N.V. , STMicroelectronics France
Inventor： Olivier Weber , Rohit Kumar Gupta , Eric Vandenbossche
IPC: H01L27/092 , H01L23/528 , H01L27/02
CPC classification number: H01L27/0928 , H01L23/528 , H01L27/0207
Abstract: An electronic device including a first active area of a first transistor, a first insulating region forming a first insulation of the first active area, a first insulating gate extending above the first active area and forming a second insulation of the first active area, and a first insulating gate contact coupled to the first insulating gate and positioned above both the first active area and the first insulating region, wherein the first insulating gate contact couples the first insulating gate to a power supply rail.
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10.发明公开公开(公告)号：US20240176863A1
公开(公告)日：2024-05-30
申请号：US18514795
申请日：2023-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Grand Quest) SAS , STMicroelectronics (Alps) SAS
Inventor： Fabrice Cheruel , Dragos Davidescu , Nicolas Anquet
Abstract: The system-on-chip includes at least one microprocessor domain including a microprocessor and at least one resource; and a resource isolation system including a filtering circuit for each resource and configured to detect a security, privilege and compartmentalization access rights violation for the resource, by transactions arriving at the resource. The filtering circuit is configured, in the event of a violation of at least one access right to the resource by a transaction, to generate a first error signal representative of the violated access right to the resource, and a second error signal representative of at least one access right of this transaction.
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