公开(公告)号：US20120139771A1

公开(公告)日：2012-06-07

申请号：US13166117

申请日：2011-06-22

申请人： Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

发明人： Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

IPC分类号： H03M1/12

CPC分类号： H03M1/468

摘要： A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

摘要翻译： 一种差分逐次逼近模数转换器，包括：比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器，所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器，所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量，其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个：第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路，其适于在采样阶段期间对差分输入电压进行采样，并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。

公开(公告)号：US20080315303A1

公开(公告)日：2008-12-25

申请号：US11767060

申请日：2007-06-22

申请人： Nicola Vannucci ,  Hubert Maier

发明人： Nicola Vannucci ,  Hubert Maier

IPC分类号： H01L29/78 ,  H01L21/311 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811

摘要： The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.

摘要翻译： 在衬底中形成半导体结构的方法包括：形成具有第一宽度W 1的第一沟槽和具有第二宽度Wc的第二沟槽，其中第一宽度We大于第二宽度Wc，沉积保护材料，衬里 所述第一沟槽覆盖所述衬底表面并填充所述第二沟槽并部分地移除所述保护材料，其中所述第二沟槽的下部保持填充有所述保护材料。

公开(公告)号：US07419883B2

公开(公告)日：2008-09-02

申请号：US11466259

申请日：2006-08-22

申请人： Nicola Vannucci ,  Sven Lanzerstorfer

发明人： Nicola Vannucci ,  Sven Lanzerstorfer

IPC分类号： H01L21/20

CPC分类号： H01L29/7813 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66166 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/8605 ,  H01L29/861

摘要： A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which lie within the trenches are doped by means of a drive-in. In one embodiment, the semiconductor structure is patterned in planar regions outside the trenches and selectively doped by an implantation process.

摘要翻译： 公开了一种在其中形成有沟槽的半导体衬底中制造具有选择性掺杂区的半导体结构的方法。 在一个实施例中，通过辅助结构的掺杂剂源，位于沟槽内的半导体结构的部分通过驱入来掺杂。 在一个实施例中，将半导体结构图案化在沟槽外部的平面区域中，并通过注入工艺选择性地掺杂。

公开(公告)号：US20070042550A1

公开(公告)日：2007-02-22

申请号：US11466259

申请日：2006-08-22

申请人： Nicola Vannucci ,  Sven Lanzerstorfer

发明人： Nicola Vannucci ,  Sven Lanzerstorfer

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66166 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/8605 ,  H01L29/861

摘要： A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which lie within the trenches are doped by means of a drive-in. In one embodiment, the semiconductor structure is patterned in planar regions outside the trenches and selectively doped by an implantation process.

摘要翻译： 公开了一种在其中形成有沟槽的半导体衬底中制造具有选择性掺杂区的半导体结构的方法。 在一个实施例中，通过辅助结构的掺杂剂源，位于沟槽内的半导体结构的部分通过驱入来掺杂。 在一个实施例中，将半导体结构图案化在沟槽外部的平面区域中，并通过注入工艺选择性地掺杂。

公开(公告)号：US08497795B2

公开(公告)日：2013-07-30

申请号：US13166117

申请日：2011-06-22

申请人： Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

发明人： Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

IPC分类号： H03M1/34

CPC分类号： H03M1/468

摘要： A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

摘要翻译： 一种差分逐次逼近模数转换器，包括：比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器，所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器，所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量，其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个：第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路，其适于在采样阶段期间对差分输入电压进行采样，并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。

公开(公告)号：US20090032906A1

公开(公告)日：2009-02-05

申请号：US11830532

申请日：2007-07-30

申请人： Thomas Ostermann ,  Nicola Vannucci

发明人： Thomas Ostermann ,  Nicola Vannucci

IPC分类号： H01L27/06 ,  H01L21/8222

CPC分类号： H01L27/0259

摘要： An electro static discharge device includes a semiconductor body. The semiconductor body includes a first surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged on the first semiconductor region and a third semiconductor region of the first conductivity type. The third semiconductor region is isolated from the first semiconductor region by the second semiconductor region. A resistor structure is arranged in the semiconductor body and comprises at least one trench structure. The resistor structure is arranged at least in the second semiconductor region and provides a high-resistance electrical connection between a first portion and a second portion of the second semiconductor region.

摘要翻译： 静电放电装置包括半导体本体。 半导体本体包括第一表面，第一导电类型的第一半导体区域，布置在第一半导体区域上的第二导电类型的第二半导体区域和第一导电类型的第三半导体区域。 第三半导体区域通过第二半导体区域与第一半导体区域隔离。 电阻器结构布置在半导体本体中并且包括至少一个沟槽结构。 电阻器结构至少布置在第二半导体区域中，并且在第二半导体区域的第一部分和第二部分之间提供高电阻电连接。

公开(公告)号：US08120135B2

公开(公告)日：2012-02-21

申请号：US12704034

申请日：2010-02-11

申请人： Norbert Krischke ,  Nicola Vannucci ,  Sven Lanzerstorfer ,  Thomas Ostermann ,  Mathias Racki ,  Markus Zundel

发明人： Norbert Krischke ,  Nicola Vannucci ,  Sven Lanzerstorfer ,  Thomas Ostermann ,  Mathias Racki ,  Markus Zundel

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L27/0207 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7821

摘要： A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.

摘要翻译： 晶体管具有具有两个或多个晶体管单元的单元阵列，集成在单元阵列中或与单元阵列相邻的温度传感器和隔离结构。 隔离结构将温度传感器与电池阵列隔离，并且具有隔离沟槽，其布置在电池阵列和温度传感器之间。 最靠近温度传感器的温度传感器和有源晶体管单元之间的距离大致对应于单元阵列内的有源晶体管单元之间的间距。

公开(公告)号：US20100207206A1

公开(公告)日：2010-08-19

申请号：US12704034

申请日：2010-02-11

申请人： Norbert Krischke ,  Nicola Vannucci ,  Sven Lanzerstorfer ,  Thomas Ostermann ,  Mathias Racki ,  Markus Zundel

发明人： Norbert Krischke ,  Nicola Vannucci ,  Sven Lanzerstorfer ,  Thomas Ostermann ,  Mathias Racki ,  Markus Zundel

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L27/0207 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7821

摘要： A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.

摘要翻译： 晶体管具有具有两个或多个晶体管单元的单元阵列，集成在单元阵列中或与单元阵列相邻的温度传感器和隔离结构。 隔离结构将温度传感器与电池阵列隔离，并且具有隔离沟槽，其布置在电池阵列和温度传感器之间。 最靠近温度传感器的温度传感器和有源晶体管单元之间的距离大致对应于单元阵列内的有源晶体管单元之间的间距。

公开(公告)号：US07718505B2

公开(公告)日：2010-05-18

申请号：US11767060

申请日：2007-06-22

申请人： Nicola Vannucci ,  Hubert Maier

发明人： Nicola Vannucci ,  Hubert Maier

IPC分类号： H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811

摘要： The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.

摘要翻译： 在衬底中形成半导体结构的方法包括：形成具有第一宽度W 1的第一沟槽和具有第二宽度Wc的第二沟槽，其中第一宽度We大于第二宽度Wc，沉积保护材料，衬里 所述第一沟槽覆盖所述衬底表面并填充所述第二沟槽并部分地移除所述保护材料，其中所述第二沟槽的下部保持填充有所述保护材料。

公开(公告)号：US20050270869A1

公开(公告)日：2005-12-08

申请号：US11132561

申请日：2005-05-19

申请人： Norbert Krischke ,  Nicola Vannucci ,  Sven Lanzerstorfer ,  Thomas Krotscheck ,  Mathias Racki ,  Markus Zundel

发明人： Norbert Krischke ,  Nicola Vannucci ,  Sven Lanzerstorfer ,  Thomas Krotscheck ,  Mathias Racki ,  Markus Zundel

IPC分类号： G11C29/00 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L27/0207 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7821

摘要： A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.

摘要翻译： 晶体管具有具有两个或多个晶体管单元的单元阵列，集成在单元阵列中或与单元阵列相邻的温度传感器和隔离结构。 隔离结构将温度传感器与电池阵列隔离，并且具有隔离沟槽，其布置在电池阵列和温度传感器之间。 最靠近温度传感器的温度传感器和有源晶体管单元之间的距离大致对应于单元阵列内的有源晶体管单元之间的间距。