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    Dynamic resistance element analog counter
    1.
    发明授权
    Dynamic resistance element analog counter 有权

    公开(公告)号：US10594299B1

    公开(公告)日：2020-03-17

    申请号：US15951196

    申请日：2018-04-12

    申请人： Senseeker Engineering Inc.

    发明人： Kenton Veeder ,  Aaron Bluestone ,  Christoph von Jutrzenka Trzebiatowski ,  Nishant Dhawan

    IPC分类号： H03H11/26 ,  H04N5/378 ,  H03K25/00

    摘要： The present disclosure provides an analog counter circuit for use in a minimal-sized circuitry. The analog counter circuit of the present disclosure can provide much higher resolution versus power consumption and layout area as compared to conventional digital counters. The analog counter circuit of the present disclosure can also provide much better bias supply management, step accuracy, multi-element step uniformity and lower supply spiking as compared to conventional analog counter architectures. The compact size of the disclosed counter circuit allows better integration of arrayed elements, such as, an array of image sensing pixels or an array of artificial neurons.

    Charge transfer circuit for compact modulators
    2.
    发明授权
    Charge transfer circuit for compact modulators 有权

    公开(公告)号：US11005495B1

    公开(公告)日：2021-05-11

    申请号：US16840198

    申请日：2020-04-03

    申请人： Senseeker Engineering Inc.

    发明人： Kenton Veeder ,  Nishant Dhawan ,  Sean McCotter

    IPC分类号： H03M1/00 ,  H03M3/00 ,  H03K3/356 ,  H04N5/378

    摘要： The present disclosure provides a current generation circuit. In one aspect, the circuit includes a current source transistor and a current sink transistor connected to the current source transistor in series, with respective sources of the current source and sink transistors being connected with each other at a common node. A voltage difference between respective gates of the current source and sink transistors defines a current value flowing through the series, the voltage difference being variable such that the current value is either time-dependent or time-independent. Respective drains of the current source and sink transistors provide a high resistance output necessary to provide a current source or sink function thereby rejecting influence of drain variation or error on the current value.

    Calibration for a single ramp multi slope analog-to-digital converter
    3.
    发明授权
    Calibration for a single ramp multi slope analog-to-digital converter 有权
    单斜坡多斜率模数转换器的校准

    公开(公告)号：US09337856B1

    公开(公告)日：2016-05-10

    申请号：US14867201

    申请日：2015-09-28

    申请人： Nishant Dhawan ,  Kenton Veeder

    发明人： Nishant Dhawan ,  Kenton Veeder

    IPC分类号： H03M1/10 ,  H03M1/06 ,  H03M1/56

    CPC分类号： H03M1/56 ,  H03M1/0697 ,  H03M1/1038 ,  H03M1/162 ,  H03M1/52 ,  H03M2201/2355

    摘要： Methods and Systems for calibrating a Single Ramp Multiple Slope Analog to Digital Converter (SRMS ADC), the ADC including a counter and a plurality N of charge and discharge elements of different time constant i.e. slope, wherein the relationships between slopes is defined as a function of the shallowest slope SN such that S1=K1·SN, S2=K2·SN, . . . SN-1=KN-1·SN-1 where the K values are integers, and the code count for conversion is C=K1·C1+K2·C2+ . . . KN-1·CN-1+CN where each Ci represents an observed counts per each slope for a conversion, including; sampling for a first calibration pass a voltage with the ADC, discharging the voltage on the steepest slope for a number of counter counts C11, charging and discharging on the remaining slopes up to K2 to KN-1 for a number of counts per slope, Ci1 e.g. C21 to CN-1,1, discharging the remaining voltage residue on the shallowest slope and note the count, CN,1, sampling the same voltage on the ADC for a second calibration pass, discharging the voltage on the steepest slope for a modified number of counter counts C12=C11+/−X, modifying the number of charge/discharge counts time Ci2 for the slopes K2 to KN-1 to adjust for the change expected from the modified steep slope discharge to reach the shallowest slope with the same expected residue as for the first calibration pass, discharging the remaining voltage residue on the shallowest slope and note the actual count, CN,2, adjusting K1 to K1a based on the difference between CN,1 and CN,2, and; using C=K1a·C1+K2·C2+ . . . KN-1·CN-1+CN as the count code for conversion.

    摘要翻译： 用于校准单斜坡多斜率模数转换器（SRMS ADC）的方法和系统，ADC包括不同时间常数即斜率的计数器和多个N个充电和放电元件，其中斜率之间的关系被定义为函数 的最小斜率SN，使得S1 = K1·SN，S2 = K2·SN。 。 。 SN-1 = KN-1·SN-1，其中K值是整数，转换代码计数为C = K1·C1 + K2·C2 +。 。 。 KN-1·CN-1 + CN，其中每个Ci表示转化每个斜率的观测计数，包括： 用于第一次校准的采样通过ADC传递电压，将最大斜率上的电压放电多个计数器计数C11，在其余斜率上的充电和放电达到K2至KN-1，对每个斜率计数Ci1 例如 C21至CN-1,1，放电最浅斜率上的剩余电压，并注意计数CN，1，对ADC进行相同的电压采样，进行第二次校准通过，将最陡坡上的电压放电至修改后的数字 计数器计数C12 = C11 +/- X，修改斜率K2至KN-1的充电/放电计数时间Ci2的数量，以调整从修改的陡倾斜放电预期的变化，以达到具有相同预期残留的最浅斜率 对于第一次校准通过，将最小斜坡上的剩余电压残余放电，并根据CN，1和CN，2之间的差值，注意实际计数CN，2调整K1至K1a; 使用C = K1a·C1 + K2·C2 +。 。 。 KN-1·CN-1 + CN作为转换计数码。