公开(公告)号：US6165895A

公开(公告)日：2000-12-26

申请号：US344865

申请日：1999-06-28

申请人： Jy-Hwang Lin

发明人： Jy-Hwang Lin

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/0276 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897

摘要： A method of fabricating an interconnect is described in which a conductive layer, an anti-reflection layer and a cover layer are sequentially formed on the substrate to form a conductive plug with its bottom situated in the anti-reflection layer. The cover layer and a portion of the anti-reflection layer and the conductive layer are remove to form an opening exposing the substrate and to define the conductive lining structures. A conformal polysilicon oxide layer is formed on the substrate and a first dielectric layer is also formed, filling the opening. A conformal isolation layer is then formed on the substrate, followed by forming a second dielectric layer covering the entire substrate. A planarization procedure is further conducted to expose the conductive plug.

摘要翻译： 描述了制造互连的方法，其中在衬底上依次形成导电层，抗反射层和覆盖层，以形成其底部位于抗反射层中的导电插塞。 去除覆盖层和防反射层和导电层的一部分以形成露出衬底并限定导电衬里结构的开口。 在基板上形成保形多晶硅氧化物层，并且还形成填充开口的第一介电层。 然后在衬底上形成保形隔离层，随后形成覆盖整个衬底的第二介电层。 进一步进行平面化处理以暴露导电插塞。

公开(公告)号：US6156655A

公开(公告)日：2000-12-05

申请号：US408612

申请日：1999-09-30

申请人： Ming-Ching Huang ,  Chih-Rong Chen ,  Kuai-Jung Ho ,  Wen-Yuan Huang ,  Chi-Chin Yeh

发明人： Ming-Ching Huang ,  Chih-Rong Chen ,  Kuai-Jung Ho ,  Wen-Yuan Huang ,  Chi-Chin Yeh

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76855 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002

摘要： A retardation layer of a copper damascene process and the fabrication method thereof, to replace the conventional barrier layer with a laminated layer. The laminated layer combines the conventional barrier layer with a porous layer, wherein the porous layer can be formed either above or below the barrier layer to improve the retardation of the copper atom diffusion. Preferably, the porous layer is formed above the barrier layer.

摘要翻译： 铜镶嵌工艺的延迟层及其制造方法，以层压层代替传统的阻挡层。 层叠层将常规阻挡层与多孔层组合，其中多孔层可以形成在阻挡层的上方或下方，以改善铜原子扩散的延迟。 优选地，多孔层形成在阻挡层上方。

公开(公告)号：US6153471A

公开(公告)日：2000-11-28

申请号：US313511

申请日：1999-05-17

申请人： Claymens Lee ,  Gary Hong

发明人： Claymens Lee ,  Gary Hong

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory. After the formation of a trench isolation structure, openings are formed, in a direction perpendicular to the orientation of the trench isolation structure, in order to form a buried bit line. A spacer is formed on the opening sidewall of the bit line in which the distance between a top of the spacer and the interface of a substrate and a pad oxide layer is the depth of the source/drain region. The opening is then filled with a doped polysilicon conducting layer used as the buried bit line. The dopant from the polysilicon conducting layer is driven into the substrate to form the source/drain region.

摘要翻译： 一种制造闪速存储器的方法。 在形成沟槽隔离结构之后，在垂直于沟槽隔离结构的取向的方向上形成开口，以便形成掩埋位线。 间隔物形成在位线的开口侧壁上，其中间隔物的顶部与衬底和衬垫氧化物层的界面之间的距离是源极/漏极区域的深度。 然后用用作掩埋位线的掺杂多晶硅导电层填充开口。 来自多晶硅导电层的掺杂剂被驱动到衬底中以形成源极/漏极区域。

公开(公告)号：US6146955A

公开(公告)日：2000-11-14

申请号：US439791

申请日：1999-11-12

申请人： Robin Lee

发明人： Robin Lee

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10873 ,  H01L27/10888 ,  H01L27/10814

摘要： A Method for forming a dynamic random access memory device with an ultra-short channel and an ultra-shallow junction is described in the invention. In the invention, the spacer is used as a mask to define the channel length of the device, so that the channel length of the device is not limited by the resolution of the photolithography process, and the performance of the device is improved thereby. Furthermore, an inversion layer serves as a junction to reduce the electric field; thus, the reliability of the device is increased.

摘要翻译： 本发明描述了一种用于形成具有超短通道和超浅结的动态随机存取存储器件的方法。 在本发明中，间隔物用作掩模以限定器件的沟道长度，使得器件的沟道长度不受光刻工艺的分辨率的限制，从而提高器件的性能。 此外，反转层用作结以减少电场; 因此，设备的可靠性增加。

公开(公告)号：US6136650A

公开(公告)日：2000-10-24

申请号：US422626

申请日：1999-10-21

申请人： Robin Lee

发明人： Robin Lee

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/1203

摘要： A three-dimensional flash array structure and the fabrication method thereof. The three-dimensional flash memory array structure disclosed in the invention can be expanded volumetrically, so that a memory cell with large capacity can be manufactured in a unit area to increase the memory capacity.

摘要翻译： 三维闪光阵列结构及其制造方法。 本发明中公开的三维闪存阵列结构可以体积扩展，从而可以在单位区域中制造具有大容量的存储单元以增加存储容量。

公开(公告)号：US6133090A

公开(公告)日：2000-10-17

申请号：US322051

申请日：1999-05-27

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/82 ,  H01L28/92 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/90 ,  Y10S438/964 ,  Y10T428/2971 ,  Y10T428/2973

摘要： A method of fabricating a capacitor. A transistor is formed on a substrate. The transistor comprises a gate and a source/drain region. A dielectric layer is formed over the substrate. A covering layer is formed on the dielectric layer. Portions of the covering layer and the dielectric layer are removed to form a contact opening. The contact opening exposes a portion of the source/drain region. A polysilicon layer is formed over the substrate to fill the contact opening. The polysilicon layer is electrically coupled with the source/drain region. A patterned photoresist layer is formed on the polysilicon layer above the contact opening. An anisotropic etching step is performed with the photoresist layer serving as a mask until a portion of the covering layer is exposed. An oxide layer is formed on the exposed covering layer. The surface of the oxide layer is higher than the surface of the polysilicon layer. The photoresist layer is removed to expose a portion of a sidewall of the polysilicon layer. A spacer is formed on the exposed sidewall of the polysilicon layer. An anisotropic etching step is performed with the spacer and the oxide layer serving as masks to remove a portion of the polysilicon layer. The spacer and the oxide layer are removed. A hemispherical grained silicon layer is formed on the polysilicon layer. A dielectric film and a conductive layer are formed over the substrate.

摘要翻译： 一种制造电容器的方法。 在基板上形成晶体管。 晶体管包括栅极和源极/漏极区域。 介电层形成在衬底上。 在电介质层上形成覆盖层。 去除覆盖层和电介质层的一部分以形成接触开口。 接触开口露出源/漏区的一部分。 在衬底上形成多晶硅层以填充接触开口。 多晶硅层与源/漏区电耦合。 在接触开口上方的多晶硅层上形成图案化的光致抗蚀剂层。 进行各向异性蚀刻步骤，其中光致抗蚀剂层用作掩模，直到覆盖层的一部分露出。 在曝光的覆盖层上形成氧化物层。 氧化物层的表面高于多晶硅层的表面。 去除光致抗蚀剂层以暴露多晶硅层的侧壁的一部分。 在多晶硅层的暴露的侧壁上形成间隔物。 使用间隔物和氧化物层作为掩模进行各向异性蚀刻步骤以去除多晶硅层的一部分。 去除间隔物和氧化物层。 在多晶硅层上形成半球状的硅层。 在衬底上形成电介质膜和导电层。

公开(公告)号：US6121151A

公开(公告)日：2000-09-19

申请号：US316585

申请日：1999-05-21

申请人： Wei-Shiau Chen

发明人： Wei-Shiau Chen

IPC分类号： G02F1/1335 ,  H01L21/00

CPC分类号： G02F1/133553

摘要： A method for fabricating a passivation layer. An isolation layer is formed on a metal layer over the substrate. The isolation layer on the metal layer is removed by chemical-mechanical polishing and dry etching. The planarization of the metal layer thus is obtained. A passivation layer having a certain structure and a thickness combination of different layers is formed over the substrate. The reflection rate of the metal layer is significantly enhanced.

摘要翻译： 一种制造钝化层的方法。 在衬底上的金属层上形成隔离层。 通过化学机械抛光和干法蚀刻去除金属层上的隔离层。 由此得到金属层的平坦化。 在衬底上形成具有一定结构和不同层的厚度组合的钝化层。 金属层的反射率显着提高。

公开(公告)号：US6103577A

公开(公告)日：2000-08-15

申请号：US213345

申请日：1998-12-17

申请人： Weiching Horng

发明人： Weiching Horng

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： A flash memory structure is formed by a method comprising the steps of providing a semiconductor substrate, and then forming a shallow first trench within the substrate. Thereafter, a buried doped region is formed underneath the first trench so that the buried doped region is at a distance from the substrate surface. The buried doped region is one major aspect in this invention that can be applied to the processing of shallow trench isolation and is capable of reducing device area. Next, a deeper second trench is etched in the substrate. The second trench has a greater depth than the depth of the first trench. Subsequently, insulating material is deposited into the first and the second trench, and then a stacked gate structure is formed above the substrate. Later, the surface source region and drain region are formed on two sides of the stacked gate structure. Through thermal operation, the surface source region alternately connects with the buried doped region to form a buried common source region.

摘要翻译： 通过包括以下步骤的方法形成闪存结构：提供半导体衬底，然后在衬底内形成浅的第一沟槽。 此后，在第一沟槽下方形成掩埋掺杂区域，使得掩埋掺杂区域距离衬底表面一定距离。 埋入掺杂区域是本发明的一个主要方面，其可以应用于浅沟槽隔离的处理，并且能够减少器件面积。 接下来，在衬底中蚀刻更深的第二沟槽。 第二沟槽具有比第一沟槽的深度更深的深度。 随后，将绝缘材料沉积到第一和第二沟槽中，然后在衬底上形成堆叠的栅极结构。 之后，表面源极区域和漏极区域形成在堆叠栅极结构的两侧。 通过热操作，表面源区域与掩埋掺杂区域交替连接以形成埋入的共源极区域。

公开(公告)号：US06096605A

公开(公告)日：2000-08-01

申请号：US76676

申请日：1998-05-12

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method of fabricating a non-volatile flash memory device, wherein a gate structure is formed on a substrate. The method includes at least the following steps. The substrate is implanted with first ions to form a source region in the substrate. A tunneling oxide layer is formed on the substrate. A silicon nitride layer is formed on the substrate. The silicon nitride is etched back to form a silicon nitride spacer on the sides of the gate structure. The substrate is implanted with second ions to form a drain region in the substrate. An oxide layer is formed over the substrate and the gate structure. Then, a polysilicon layer is formed on the oxide layer. The gate structure is used as a selection gate, the silicon nitride spacer is used to store electrons, and the polysilicon layer is used as a controlling gate. The flash memory device can free memory cells by from the influences of over-erased effect.

摘要翻译： 一种制造非挥发性闪速存储器件的方法，其中栅极结构形成在衬底上。 该方法至少包括以下步骤。 用衬底注入第一离子以在衬底中形成源区。 在衬底上形成隧道氧化物层。 在衬底上形成氮化硅层。 将氮化硅回蚀刻以在栅极结构的侧面上形成氮化硅间隔物。 用第二离子注入衬底以在衬底中形成漏区。 在衬底和栅极结构之上形成氧化物层。 然后，在氧化物层上形成多晶硅层。 栅极结构用作选择栅极，氮化硅间隔物用于存储电子，多晶硅层用作控制栅极。 闪存器件可以通过过度擦除效应的影响来释放存储器单元。

公开(公告)号：US6069058A

公开(公告)日：2000-05-30

申请号：US924432

申请日：1997-08-27

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76237

摘要： A shallow trench isolation structure is formed by providing a pad layer and a silicon nitride polish stop layer on a surface of a P-type silicon substrate. The silicon nitride polish stop layer and the pad oxide layer are patterned to define openings corresponding to portions of the substrate that will be etched to form trenches. Trenches are defined in the P-type silicon substrate by anisotropic etching. A boron doped oxide or glass is deposited along the walls and floor of the trench. An undoped TEOS oxide is provided over the doped oxide or glass to complete filling of the trench. The device is subjected to a high temperature reflow process, causing the dielectric materials to flow, partially planarizing the device and causing the boron of the first layer to diffuse into the walls and floor of the trench. Chemical mechanical polishing removes excess portions of the dielectric layers. The silicon nitride polish stop layer and the pad oxide layer are removed and conventional processing is performed to complete devices on the substrate. Diffusion of boron into the walls of the trench forms a self-aligned field doping region for the shallow trench isolation structure using relatively few processing steps.

摘要翻译： 通过在P型硅衬底的表面上设置焊盘层和氮化硅抛光停止层来形成浅沟槽隔离结构。 图案化氮化硅抛光停止层和焊盘氧化物层以限定对应于将被蚀刻以形成沟槽的衬底的部分的开口。 通过各向异性蚀刻在P型硅衬底中限定沟槽。 硼掺杂的氧化物或玻璃沿着沟槽的壁和底部沉积。 在掺杂的氧化物或玻璃上提供未掺杂的TEOS氧化物以完成沟槽的填充。 对器件进行高温回流处理，使电介质材料流动，使器件局部平坦化，并使第一层的硼扩散到沟槽的壁和底部。 化学机械抛光除去介电层的多余部分。 去除氮化硅抛光停止层和焊盘氧化物层，并进行常规处理以完成衬底上的器件。 使用相对较少的加工步骤将硼扩散到沟槽的壁中形成用于浅沟槽隔离结构的自对准场掺杂区域。