公开(公告)号：US08385111B2

公开(公告)日：2013-02-26

申请号：US12844712

申请日：2010-07-27

申请人： Dong Keun Kim

发明人： Dong Keun Kim

IPC分类号： G11C11/00

CPC分类号： G11C7/18 ,  G11C13/0004 ,  G11C13/0023

摘要： A semiconductor memory apparatus includes a plurality of unit cell arrays having a plurality of word lines which are disposed in a row direction and a plurality of global bit lines which are disposed in a column direction; a row decoder configured to activate at least two word lines among the plurality of word lines in response to a row address which designates one word line; a global column switch block configured to select two different global bit lines among the plurality of global bit lines in response to column control signals; and a column decoder configured to generate the column control signals in response to a column address.

摘要翻译： 一种半导体存储装置，具有：多个单元阵列，具有排列成行方向的多个字线和沿列方向配置的多个全局位线; 行解码器，其被配置为响应于指定一个字线的行地址来激活所述多个字线中的至少两个字线; 全局列切换块，被配置为响应于列控制信号选择多个全局位线中的两个不同的全局位线; 以及列解码器，被配置为响应于列地址而生成列控制信号。

公开(公告)号：US08369124B2

公开(公告)日：2013-02-05

申请号：US12964182

申请日：2010-12-09

申请人： Myoung Jin Lee

发明人： Myoung Jin Lee

IPC分类号： G11C5/06

CPC分类号： G11C7/18 ,  G11C7/062

摘要： Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.

摘要翻译： 公开了一种半导体存储装置，包括上层和下层，其间具有读出放大器阵列区域，其中读出放大器阵列区域包括多个读出放大器。 还存在多个位线，其被配置为从上垫子朝着读出放大器阵列区域延伸，并且多个互补位线被配置为从下垫子朝着读出放大器阵列区域延伸。 上层的位线和下层的互补位线被配置为在感测放大器阵列区域中以预定间隔交替布置，并且读出放大器被配置为形成在位线和相应的互补位线 。

公开(公告)号：US08367550B2

公开(公告)日：2013-02-05

申请号：US12978832

申请日：2010-12-27

申请人： Jong Bum Park ,  Chun Ho Kang ,  Young Seung Kim

发明人： Jong Bum Park ,  Chun Ho Kang ,  Young Seung Kim

IPC分类号： H01L21/44

CPC分类号： H01L27/10888 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/28525 ,  H01L23/485 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber.

摘要翻译： 导电层可以通过将硅衬底加载到内部温度处于约250℃至约300℃范围内的负载温度的室中而在半导体衬底上制造，从而增加室的内部温度 从加载温度到加工温度，并且通过将硅源气体和杂质源气体提供到室中，其中腔室可以是例如在硅衬底上顺序地堆叠单晶硅层和多晶硅层 ，CVD室或LPCVD室。

公开(公告)号：US10396168B2

公开(公告)日：2019-08-27

申请号：US16010080

申请日：2018-06-15

申请人： SK hynix Inc.

发明人： Dae Sung Eom ,  Jeong Sang Kang

IPC分类号： H01L29/423 ,  H01L27/11582

摘要： There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes a pipe gate stack structure in which a portion of a first channel layer is buried. The semiconductor device includes the pipe gate stack structure in which a portion of a second channel layer is buried. The semiconductor device configured to individually control the first and second channel layers.

公开(公告)号：US10803915B1

公开(公告)日：2020-10-13

申请号：US16721348

申请日：2019-12-19

申请人： SK hynix Inc.

发明人： Woongrae Kim

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4076

摘要： A semiconductor device includes a pre-shift circuit and a shift circuit. The pre-shift circuit shifts an internal write signal by a pre-shift period to generate a pre-write signal. The shift circuit shifts the pre-write signal by a shift period to generate a shift write signal for generating a column selection signal. The column selection signal is activated to select a column path through which data are inputted or outputted. The pre-shift period is set as a period corresponding to a multiple of “L” times a cycle of a clock signal, wherein “L” is a natural number which is equal to or greater than two.