公开(公告)号：US08367550B2

公开(公告)日：2013-02-05

申请号：US12978832

申请日：2010-12-27

申请人： Jong Bum Park ,  Chun Ho Kang ,  Young Seung Kim

发明人： Jong Bum Park ,  Chun Ho Kang ,  Young Seung Kim

IPC分类号： H01L21/44

CPC分类号： H01L27/10888 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/28525 ,  H01L23/485 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber.

摘要翻译： 导电层可以通过将硅衬底加载到内部温度处于约250℃至约300℃范围内的负载温度的室中而在半导体衬底上制造，从而增加室的内部温度 从加载温度到加工温度，并且通过将硅源气体和杂质源气体提供到室中，其中腔室可以是例如在硅衬底上顺序地堆叠单晶硅层和多晶硅层 ，CVD室或LPCVD室。

公开(公告)号：US20110159676A1

公开(公告)日：2011-06-30

申请号：US12978832

申请日：2010-12-27

申请人： Jong Bum PARK ,  Chun Ho KANG ,  Young Seung KIM

发明人： Jong Bum PARK ,  Chun Ho KANG ,  Young Seung KIM

IPC分类号： H01L21/30 ,  G06F19/00

CPC分类号： H01L27/10888 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/28525 ,  H01L23/485 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber.

摘要翻译： 导电层可以通过将硅衬底加载到内部温度处于约250℃至约300℃范围内的负载温度的室中而在半导体衬底上制造，从而增加室的内部温度 从加载温度到加工温度，并且通过将硅源气体和杂质源气体提供到室中，其中腔室可以是例如在硅衬底上顺序地堆叠单晶硅层和多晶硅层 ，CVD室或LPCVD室。

公开(公告)号：US07548485B2

公开(公告)日：2009-06-16

申请号：US11845191

申请日：2007-08-27

申请人： Young-Seung Kim ,  Chul-Sung Park

发明人： Young-Seung Kim ,  Chul-Sung Park

IPC分类号： G11C8/02

CPC分类号： G11C11/413

摘要： A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.

摘要翻译： 提供能够进行同步/异步操作的半导体存储器件及其数据输入/输出方法。 半导体存储器件包括存储单元阵列，外围电路，被配置为向存储单元阵列中的单元写入数据并从单元读取数据;以及旁路控制单元，被配置为控制延迟写入操作和旁路操作 外围电路根据半导体存储器件的模式转换。 因此，可以保持数据一致性。 此外，可以通过仅响应于时钟信号的切换而产生模式转换信号来防止在模式转换期间可能发生的伪周期时间。

公开(公告)号：US07499310B2

公开(公告)日：2009-03-03

申请号：US11332605

申请日：2006-01-13

申请人： Chul-Sung Park ,  Young-Seung Kim

发明人： Chul-Sung Park ,  Young-Seung Kim

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C7/12 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/005

摘要： There is provided a bit line voltage supply circuit for reducing leakage current flowing from bit lines to a memory cell without substantially deteriorating the performance of a semiconductor memory device. A bit line voltage switch applies a first supply voltage to a bit line pair in response to a first switch control signal, and applies a second supply voltage having a lower voltage than the first supply voltage to the bit line pair in response to a second switch control signal. A bit line voltage controller controls the first and second switch control signals so that the second supply voltage is supplied to the bit line pair during a standby mode, and the first supply voltage is supplied to the bit line pair when the semiconductor memory device changes from the standby mode to an operational mode for a predetermined time period.

摘要翻译： 提供了一种位线电压供应电路，用于减少从位线流向存储单元的泄漏电流，而不会显着降低半导体存储器件的性能。 位线电压开关响应于第一开关控制信号向位线对施加第一电源电压，并响应于第二开关将比第一电源电压低的电压施加到位线对 控制信号。 位线电压控制器控制第一和第二开关控制信号，使得在待机模式期间第二电源电压被提供给位线对，并且当半导体存储器件从 待机模式进入操作模式达预定时间段。

公开(公告)号：US20080165610A1

公开(公告)日：2008-07-10

申请号：US11845191

申请日：2007-08-27

申请人： Young-Seung KIM ,  Chul-Sung PARK

发明人： Young-Seung KIM ,  Chul-Sung PARK

IPC分类号： G11C8/00

CPC分类号： G11C11/413

摘要： A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.

摘要翻译： 提供能够进行同步/异步操作的半导体存储器件及其数据输入/输出方法。 半导体存储器件包括存储单元阵列，外围电路，被配置为向存储单元阵列中的单元写入数据并从单元读取数据;以及旁路控制单元，被配置为控制延迟写入操作和旁路操作 外围电路根据半导体存储器件的模式转换。 因此，可以保持数据一致性。 此外，可以通过仅响应于时钟信号的切换而产生模式转换信号来防止在模式转换期间可能发生的伪周期时间。

公开(公告)号：US06914462B2

公开(公告)日：2005-07-05

申请号：US10440685

申请日：2003-05-19

申请人： Young-Seung Kim ,  Young-Dae Lee

发明人： Young-Seung Kim ,  Young-Dae Lee

IPC分类号： G06F1/24 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： There is provided a power-on reset circuit and method for a semiconductor integrated circuit device using a plurality of power sources, in which a power-on reset operation is stable and reliable, where the power-on reset circuit includes voltage detection circuits for generating at least two voltage detection signals with respect to the power sources, the power-on reset circuit generates a plurality of power-on reset signals using combination logic circuits for performing logic operations of the voltage detection signals, and internal latches and flip-flops are stably reset in response to the plurality of power-on reset signals.

摘要翻译： 提供了一种使用多个电源的半导体集成电路装置的上电复位电路和方法，其中上电复位操作是稳定和可靠的，其中上电复位电路包括用于产生电压的电压检测电路 相对于电源的至少两个电压检测信号，上电复位电路使用用于执行电压检测信号的逻辑运算的组合逻辑电路产生多个上电复位信号，并且内部锁存器和触发器是 响应于多个上电复位信号稳定复位。

公开(公告)号：US20060158943A1

公开(公告)日：2006-07-20

申请号：US11332605

申请日：2006-01-13

申请人： Chul-Sung Park ,  Young-Seung Kim

发明人： Chul-Sung Park ,  Young-Seung Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/005

摘要： There is provided a bit line voltage supply circuit for reducing leakage current flowing from bit lines to a memory cell without substantially deteriorating the performance of a semiconductor memory device. A bit line voltage switch applies a first supply voltage to a bit line pair in response to a first switch control signal, and applies a second supply voltage having a lower voltage than the first supply voltage to the bit line pair in response to a second switch control signal. A bit line voltage controller controls the first and second switch control signals so that the second supply voltage is supplied to the bit line pair during a standby mode, and the first supply voltage is supplied to the bit line pair when the semiconductor memory device changes from the standby mode to an operational mode for a predetermined time period.

公开(公告)号：US20080072121A1

公开(公告)日：2008-03-20

申请号：US11750527

申请日：2007-05-18

申请人： Seung-min Lee ,  Chul-sung Park ,  Young-seung Kim ,  Byeong-uk Yoo

发明人： Seung-min Lee ,  Chul-sung Park ,  Young-seung Kim ,  Byeong-uk Yoo

IPC分类号： G06F11/16

CPC分类号： G11C29/812 ,  G11C29/806 ,  G11C29/808

摘要： A method and apparatus for repairing defective cells for each section word line. The repairing apparatus includes an address comparison unit and a repairing unit. The address comparison unit compares a main address of a defective address, indicating the location of a defective cell, to a main address of an external address. The address comparison unit determines when a redundancy main word line corresponding to the main address of the external address is activated. The repairing unit activates a redundancy section word line corresponding to a section address of the external address from among a plurality of redundancy section word lines connected to the redundancy main word line in order to repair the defective cell. Accordingly, defective cells are repaired for each section word line while minimizing the area of the repairing apparatus. Randomly generated defective cells can be efficiently repaired.

摘要翻译： 一种用于修复每个部分字线的有缺陷的单元的方法和装置。 修理装置包括地址比较单元和修理单元。 地址比较单元将指示缺陷单元的位置的缺陷地址的主地址与外部地址的主地址进行比较。 地址比较单元确定何时激活对应于外部地址的主地址的冗余主字线。 修复单元从与冗余主字线连接的多个冗余部分字线中激活对应于外部地址的部分地址的冗余部分字线，以便修复有缺陷的单元。 因此，对于每个部分字线修复有缺陷的单元，同时最小化修复装置的面积。 随机产生的有缺陷的细胞可以被有效地修复。