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    Technology For Providing Out-Of-Band Processor Telemetry
    1.
    发明申请
    Technology For Providing Out-Of-Band Processor Telemetry 审中-公开

    公开(公告)号：US20200349045A1

    公开(公告)日：2020-11-05

    申请号：US16400063

    申请日：2019-05-01

    申请人： Johan Gerard Van De Groenendaal ,  Ahmad Yasin ,  Alexander Gendler

    发明人： Johan Gerard Van De Groenendaal ,  Ahmad Yasin ,  Alexander Gendler

    IPC分类号： G06F11/30 ,  G06F11/34

    摘要： An integrated circuit includes technology for providing out-of-band (OOB) processor telemetry. The integrated circuit comprises a processor comprising a core and a distributed core perimeter. The integrated circuit also comprises a telemetry push agent in the distributed core perimeter, and an OOB telemetry manager in the core to operate out of band and to send telemetry data for the processor to the telemetry push agent. The telemetry push agent comprises control logic to (a) receive the telemetry data from the OOB telemetry manager and (b) forward at least some of the telemetry data to in-band telemetry software. Other embodiments are described and claimed.

    ELAPSED CYCLE TIMER IN LAST BRANCH RECORDS
    3.
    发明申请
    ELAPSED CYCLE TIMER IN LAST BRANCH RECORDS 有权
    最近分支记录中的ELAPSED循环定时器

    公开(公告)号：US20140380027A1

    公开(公告)日：2014-12-25

    申请号：US13922421

    申请日：2013-06-20

    申请人： Ahmad Yasin ,  Michael W. Chynoweth ,  Ofer Levy ,  Jason W. Brandt ,  Angela Schmid

    发明人： Ahmad Yasin ,  Michael W. Chynoweth ,  Ofer Levy ,  Jason W. Brandt ,  Angela Schmid

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3806 ,  G06F9/30058 ,  G06F9/30098 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/865 ,  G06F2201/88

    摘要： A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device and an LBR structure communicably coupled to the LBR counter. The LBR structure comprises a plurality of LBR entries. Furthermore, an LBR entry of the plurality of LBR entries comprises an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter when the LBR entry is created.

    摘要翻译： 公开了一种在最后的分支记录（LBR）中实现经过周期定时器的处理装置。 本公开的处理装置包括与处理装置的每个周期重复的最后一个分支记录（LBR）计数器和可通信地耦合到LBR计数器的LBR结构。 LBR结构包括多个LBR条目。 此外，多个LBR条目的LBR条目包括由处理装置执行的分支指令的地址指令指针（IP），分支指令的目标的地址IP以及存储分支指令的值的经过时间字段 当创建LBR条目时，LBR计数器。

    PERFORMANCE SCALABILITY PREDICTION
    5.
    发明申请
    PERFORMANCE SCALABILITY PREDICTION 有权
    性能规模预测

    公开(公告)号：US20150277538A1

    公开(公告)日：2015-10-01

    申请号：US14225960

    申请日：2014-03-26

    申请人： AHMAD YASIN ,  NIR ROSENZWEIG ,  ELIEZER WEISSMANN ,  EFRAIM EFI ROTEM

    发明人： AHMAD YASIN ,  NIR ROSENZWEIG ,  ELIEZER WEISSMANN ,  EFRAIM EFI ROTEM

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3243 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/152

    摘要： A processing device implementing performance scalability prediction is disclosed. A processing device of the disclosure includes a first counter to increment with each cycle of the processing device in which threads of the processing device are active. The processing device further includes a second counter to increment with each cycle of the processing device in which execution units of the processing device are stalled for one of the threads, and an access request from the one of the threads to memory external to the processing device is pending.

    摘要翻译： 公开了一种实现性能可伸缩性预测的处理装置。 本公开的处理装置包括：第一计数器，其随处理装置的每个周期递增，其中处理装置的线程处于活动状态。 所述处理装置还包括第二计数器，其随着所述处理装置的每个周期递增，其中所述处理装置的执行单元被停止用于所述线程之一，以及从所述线程中的一个到所述处理装置外部的存储器的访问请求 等待中。

    INSTRUCTION AND LOGIC FOR ADAPTIVE EVENT-BASED SAMPLING
    6.
    发明申请
    INSTRUCTION AND LOGIC FOR ADAPTIVE EVENT-BASED SAMPLING 审中-公开
    自适应事件采样的指令和逻辑

    公开(公告)号：US20160019062A1

    公开(公告)日：2016-01-21

    申请号：US14332736

    申请日：2014-07-16

    申请人： Ahmad Yasin ,  Peggy J. Irelan ,  Grant G. Zhou

    发明人： Ahmad Yasin ,  Peggy J. Irelan ,  Grant G. Zhou

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30036 ,  G06F9/3887

    摘要： A processor includes a core and an event-based sampler. The core includes logic to execute and retire an instruction. The event-based sampler includes logic determine a subset of a plurality of execution data of the processor from a register. The register includes bits specifying a subset of execution data. The event-based sampler further includes logic to selectively collect the determined subset of execution data upon retirement of the instruction and to store the selectively collected execution data.

    摘要翻译： 处理器包括核心和基于事件的采样器。 核心包括执行和退出指令的逻辑。 基于事件的采样器包括从寄存器确定处理器的多个执行数据的子集的逻辑。 寄存器包括指定执行数据子集的位。 基于事件的采样器还包括在退出指令时选择性地收集确定的执行数据子集并存储有选择地收集的执行数据的逻辑。

    Causing an interrupt based on event count
    7.
    发明授权
    Causing an interrupt based on event count 有权
    导致基于事件计数的中断

    公开(公告)号：US09575766B2

    公开(公告)日：2017-02-21

    申请号：US13991878

    申请日：2011-12-29

    申请人： Ahmad Yasin ,  Peggy J. Irelan ,  Ofer Levy ,  Emile Ziedan ,  Grant Zhou

    发明人： Ahmad Yasin ,  Peggy J. Irelan ,  Ofer Levy ,  Emile Ziedan ,  Grant Zhou

    IPC分类号： G06F9/38 ,  G06F11/34

    CPC分类号： G06F9/3861 ,  G06F11/3466 ,  G06F11/3476 ,  G06F2201/86 ,  G06F2201/88

    摘要： Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.

    摘要翻译： 一些实现提供了响应于多个事件的发生而在处理器中引起中断的技术和布置。 第一事件计数器对处理器内事件类型的发生进行计数，并响应于达到第一预定义计数而输出信号以激活第二事件计数器。 第二事件计数器对处理器内的事件类型的发生进行计数，并响应于达到第二预定义计数而导致处理器的中断。

    CAUSING AN INTERRUPT BASED ON EVENT COUNT
    8.
    发明申请
    CAUSING AN INTERRUPT BASED ON EVENT COUNT 有权
    导致基于事件计数的中断

    公开(公告)号：US20140013091A1

    公开(公告)日：2014-01-09

    申请号：US13991878

    申请日：2011-12-29

    申请人： Ahmad Yasin ,  Peggy J. Irelan ,  Ofer Levy ,  Emile Ziedan ,  Grant Zhou

    发明人： Ahmad Yasin ,  Peggy J. Irelan ,  Ofer Levy ,  Emile Ziedan ,  Grant Zhou

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3861 ,  G06F11/3466 ,  G06F11/3476 ,  G06F2201/86 ,  G06F2201/88

    摘要： Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.

    摘要翻译： 一些实现提供了响应于多个事件的发生而在处理器中引起中断的技术和布置。 第一事件计数器对处理器内事件类型的发生进行计数，并响应于达到第一预定义计数而输出信号以激活第二事件计数器。 第二事件计数器对处理器内的事件类型的发生进行计数，并响应于达到第二预定义计数而导致处理器的中断。