INSTRUCTION AND LOGIC FOR ADAPTIVE EVENT-BASED SAMPLING
    1.
    发明申请
    INSTRUCTION AND LOGIC FOR ADAPTIVE EVENT-BASED SAMPLING 审中-公开
    自适应事件采样的指令和逻辑

    公开(公告)号:US20160019062A1

    公开(公告)日:2016-01-21

    申请号:US14332736

    申请日:2014-07-16

    IPC分类号: G06F9/30

    摘要: A processor includes a core and an event-based sampler. The core includes logic to execute and retire an instruction. The event-based sampler includes logic determine a subset of a plurality of execution data of the processor from a register. The register includes bits specifying a subset of execution data. The event-based sampler further includes logic to selectively collect the determined subset of execution data upon retirement of the instruction and to store the selectively collected execution data.

    摘要翻译: 处理器包括核心和基于事件的采样器。 核心包括执行和退出指令的逻辑。 基于事件的采样器包括从寄存器确定处理器的多个执行数据的子集的逻辑。 寄存器包括指定执行数据子集的位。 基于事件的采样器还包括在退出指令时选择性地收集确定的执行数据子集并存储有选择地收集的执行数据的逻辑。

    Causing an interrupt based on event count
    2.
    发明授权
    Causing an interrupt based on event count 有权
    导致基于事件计数的中断

    公开(公告)号:US09575766B2

    公开(公告)日:2017-02-21

    申请号:US13991878

    申请日:2011-12-29

    IPC分类号: G06F9/38 G06F11/34

    摘要: Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.

    摘要翻译: 一些实现提供了响应于多个事件的发生而在处理器中引起中断的技术和布置。 第一事件计数器对处理器内事件类型的发生进行计数,并响应于达到第一预定义计数而输出信号以激活第二事件计数器。 第二事件计数器对处理器内的事件类型的发生进行计数,并响应于达到第二预定义计数而导致处理器的中断。

    CAUSING AN INTERRUPT BASED ON EVENT COUNT
    3.
    发明申请
    CAUSING AN INTERRUPT BASED ON EVENT COUNT 有权
    导致基于事件计数的中断

    公开(公告)号:US20140013091A1

    公开(公告)日:2014-01-09

    申请号:US13991878

    申请日:2011-12-29

    IPC分类号: G06F9/38

    摘要: Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.

    摘要翻译: 一些实现提供了响应于多个事件的发生而在处理器中引起中断的技术和布置。 第一事件计数器对处理器内事件类型的发生进行计数,并响应于达到第一预定义计数而输出信号以激活第二事件计数器。 第二事件计数器对处理器内的事件类型的发生进行计数,并响应于达到第二预定义计数而导致处理器的中断。

    PERFORMANCE MONITORING RESOURCES PROGRAMMED STATUS
    8.
    发明申请
    PERFORMANCE MONITORING RESOURCES PROGRAMMED STATUS 有权
    性能监测资源编程状态

    公开(公告)号:US20130332933A1

    公开(公告)日:2013-12-12

    申请号:US13995566

    申请日:2011-12-28

    IPC分类号: G06F9/54

    摘要: A system and method for a performance monitoring hardware unit that may include logic to poll one or more performance monitoring shared resources and determine a status of each performance monitoring shared resource. The performance monitoring hardware unit may also include an interface to provide the status to allow programming of the one or more performance monitoring shared resource. The status may correspond to a usage and/or an errata condition. Thus, the performance monitoring hardware unit may prevent programming conflicts of the one or more performance monitoring shared resources.

    摘要翻译: 用于性能监视硬件单元的系统和方法,其可以包括用于轮询一个或多个性能监视共享资源并确定每个性能监视共享资源的状态的逻辑。 性能监视硬件单元还可以包括提供状态以允许编程一个或多个性能监视共享资源的接口。 该状态可以对应于使用和/或勘误条件。 因此,性能监视硬件单元可以防止一个或多个性能监视共享资源的编程冲突。

    Performance monitoring of shared processing resources

    公开(公告)号:US09720744B2

    公开(公告)日:2017-08-01

    申请号:US13995566

    申请日:2011-12-28

    IPC分类号: G06F9/46 G06F9/54 G06F11/34

    摘要: A system and method for a performance monitoring hardware unit that may include logic to poll one or more performance monitoring shared resources and determine a status of each performance monitoring shared resource. The performance monitoring hardware unit may also include an interface to provide the status to allow programming of the one or more performance monitoring shared resource. The status may correspond to a usage and/or an errata condition. Thus, the performance monitoring hardware unit may prevent programming conflicts of the one or more performance monitoring shared resources.