摘要:
Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.
摘要:
Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.
摘要:
A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.
摘要:
A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device and an LBR structure communicably coupled to the LBR counter. The LBR structure comprises a plurality of LBR entries. Furthermore, an LBR entry of the plurality of LBR entries comprises an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter when the LBR entry is created.
摘要:
A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.
摘要:
The present invention is related to peptides, which are suitable for use as cell-penetrating peptides (CPPs), variants thereof and/or complexes, fusion molecules and/or conjugates comprising same, use thereof for manufacture of compositions for diagnosing, treating and/or preventing of medical conditions.
摘要:
Provided are angiopoietin-derived peptides or homologs or derivatives thereof, pharmaceutical composition including them, a use thereof for therapy and for the manufacture of a medicament, a method of treating a wide range of conditions, disorders and diseases therewith, nucleotide sequences encoding them, antibodies directed to epitopes thereof and fusion proteins including them.
摘要:
Disclosed herein are methods for determining the likelihood of a subject to develop Acute graft versus host disease (aGVHD) upon receiving myeloablative allogeneic hematopoietic stem cell transplantation (HSCT). One such method comprises assaying for baseline plasma concentration of RANTES in a sample obtained from the subject, and comparing the baseline plasma concentration of RANTES to a predetermined level. The method may further comprise assaying for day 7 plasma concentration of RANTES in sample obtained from the subject, and comparing the day 7 plasma concentration of RANTES to a predetermined level. Another such method comprises assaying for day 7 plasma concentration of RANTES in a sample obtained from the subject, and comparing the day 7 plasma concentration of RANTES to a predetermined level. Another such method comprises assaying for donor plasma concentration of RANTES in a sample obtained from a donor of the hemtopoietic stem cells, and comparing the donor plasma concentration of RANTES to a predetermined level, wherein a donor plasma concentration of RANTES less than the predetermined level indicates a likelihood of the subject to develop aGVHD upon receiving myeloablative allogeneic HSCT from that donor. Other methods include assaying for day 0, or for day 7, plasma concentration of MCP-1 in a sample obtained from the subject, and comparing the day 0 or day 7, plasma concentration of MCP-1 to a predetermined level.
摘要:
This invention relates to a novel target for production of immune and non-immune based therapeutics and for disease diagnosis. More particularly, the invention provides therapeutic antibodies against KRTCAP3, FAM26F, MGC52498, FAM70A or TMEM154 antigens, which are differentially expressed in cancer, and diagnostic and therapeutic usages. This invention further relates to extracellular domains of KRTCAP3, FAM26F, MGC52498, FAM70A and TMEM154 proteins and variants, and therapeutic usages thereof.
摘要:
In one embodiment, the present invention includes a retirement unit to receive and retire executed instructions. The retirement unit may include a first array to receive information at allocation and a second array to receive information after execution. The retirement unit may further include logic to calculate an event associated with an executed instruction if information associated with the executed instruction is stored in an on-demand portion of at least one of arrays. Other embodiments are described and claimed.