摘要:
A data processing apparatus which sequentially executes a verification process so as to recognize a target object, comprising: an obtaining unit configured to obtain dictionary data to be referred to in the verification process; a holding unit configured to hold a plurality of dictionary data; a verification unit configured to execute the verification process for the input data by referring to one dictionary data; a history holding unit configured to hold a verification result; and a prefetch determination unit configured to determine based on the verification result whether to execute prefetch processing in which the obtaining unit obtains in advance dictionary data to be referred to by the verification unit in a succeeding verification process, and holds the dictionary data in the holding unit before the succeeding verification process.
摘要:
According to the present invention, a phase shift of data received by an external device controller is delayed and corrected, and a control signal used for the data load control on the external device controller side is delayed period-by-period. Further, the phase shift is adjusted and then the control signal is adjusted. The adjustment can beneficially be performed very quickly. Moreover, the present invention is also beneficial for preventing a failure to load data.
摘要:
A packet accompanying data valid information is transferred at high efficiency within an integrated circuit or between integrated circuits. A character indicating data enable information is provided and an identifier indicating a data enable character is assigned onto the packet. When the data enable information is valid in series, the data enable characters are eliminated from the packet to be transferred.
摘要:
An information processing apparatus for processing input data using multiple items of reference data in succession is provided. The apparatus includes a secondary storage unit configured to store the reference data; a primary storage unit accessible at a speed higher than that of the secondary storage unit; a read-out unit configured to read out the reference data from the secondary storage unit to the primary storage unit; an execution unit configured to execute processing of the input data using the reference data in the primary storage unit; a determination unit configured to determine, based upon at least one of a probability that reference data scheduled for use by the execution unit will change and quantity of the scheduled reference data, whether the scheduled reference data is to be prefetched; and a control unit configured to control prefetch based on the result of determination of the determination unit.
摘要:
A packet accompanying data valid information is transferred at high efficiency within an integrated circuit or between integrated circuits. A character indicating data enable information is provided and an identifier indicating a data enable character is assigned onto the packet. When the data enable information is valid in series, the data enable characters are eliminated from the packet to be transferred.
摘要:
If data received by the an information processing apparatus from an external device is delayed by one cycle or more with respect to a clock of the information processing apparatus, the information processing apparatus may require an additional process for adjusting a data latch timing.Delay information indicating a relationship between a calibration pattern to be received and an amount of cycle delay is stored in advance. Thus, the time required for detecting an amount of cycle delay, which is equivalent to the amount by which a signal for controlling a data latch mechanism in the information processing apparatus to stop its operation is delayed, can be reduced.
摘要:
If data received by the an information processing apparatus from an external device is delayed by one cycle or more with respect to a clock of the information processing apparatus, the information processing apparatus may require an additional process for adjusting a data latch timing.Delay information indicating a relationship between a calibration pattern to be received and an amount of cycle delay is stored in advance. Thus, the time required for detecting an amount of cycle delay, which is equivalent to the amount by which a signal for controlling a data latch mechanism in the information processing apparatus to stop its operation is delayed, can be reduced.
摘要:
If data received by an external device controller from an external device is delayed by one cycle or more with respect to an output clock of the external device controller, a delay may not necessarily be detected with an existing configuration.When a data latch timing of the external device controller is adjusted, gating of or releasing gating of an output clock of the external device controller is performed in accordance with predetermined gating information, thus improving the accuracy of calibration for adjusting the data latch timing.
摘要:
An image recognition apparatus that recognizes an object related to a certain object in an image sequentially recognizes an object from the image in accordance with recognition-order information that indicates an object order in an object sequence including the certain object, the related object, and an object connected between those objects. The apparatus determines whether or not an object recognized in a current turn of recognition has a connective relationship with an extracted object obtained in a previous turn of recognition, and obtains the object that has been determined as having a connective relationship as an extracted object. Based on an object extracted by a repetition of the above processing, that is, recognition, connective relationship determination, and obtaining, in the above-described recognition order, the related object is associated with the certain object.
摘要:
If data received by an external device controller from an external device is delayed by one cycle or more with respect to an output clock of the external device controller, a delay may not necessarily be detected with an existing configuration.When a data latch timing of the external device controller is adjusted, gating of or releasing gating of an output clock of the external device controller is performed in accordance with predetermined gating information, thus improving the accuracy of calibration for adjusting the data latch timing.