公开(公告)号：US07327227B2

公开(公告)日：2008-02-05

申请号：US10542282

申请日：2004-11-04

申请人： Kiyokazu Ohtaki ,  Toru Maeda ,  Hisashi Kato ,  Akiyoshi Osumi ,  Takeshi Kumazaki ,  Ifushi Shimonomoto ,  Toshio Shimomura ,  Yoshinori Fukuoka ,  Koichi Masamura

发明人： Kiyokazu Ohtaki ,  Toru Maeda ,  Hisashi Kato ,  Akiyoshi Osumi ,  Takeshi Kumazaki ,  Ifushi Shimonomoto ,  Toshio Shimomura ,  Yoshinori Fukuoka ,  Koichi Masamura

IPC分类号： B60R25/10

CPC分类号： B60R25/24 ,  B60R25/04

摘要： A vehicle security device for improving the security level of a vehicle. The vehicle security device is connected to an engine and communicates with a portable device. A smart ECU performs a first coded communication to establish mutual authentication with the portable device. An ID code box is connected to the smart ECU, has a first code and a second code, and does not communicate with the portable device. The ID code box performs a second coded communication using the first code to establish a second mutual authentication with the smart ECU. An engine ECU performs a third coded communication using the second code to establish a third mutual authentication with the ID code box. The engine ECU enables the engine to be started when every one of the first, second, and third mutual authentications are established.

摘要翻译： 一种用于改善车辆安全级别的车辆安全装置。 车辆安全装置连接到发动机并与便携式装置通信。 智能ECU执行第一编码通信以建立与便携式设备的相互认证。 ID代码框连接到智能ECU，具有第一代码和第二代码，并且不与便携式设备通信。 ID代码框使用第一代码执行第二编码通信，以与智能ECU建立第二相互认证。 发动机ECU使用第二代码执行第三编码通信，以与ID代码框建立第三相互认证。 当建立第一，第二和第三相互认证中的每一个时，发动机ECU使发动机能够启动。

公开(公告)号：US06275902B1

公开(公告)日：2001-08-14

申请号：US09188693

申请日：1998-11-10

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F1208

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

摘要翻译： 数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。 经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。 高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。 基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

公开(公告)号：US5363332A

公开(公告)日：1994-11-08

申请号：US860442

申请日：1992-03-30

申请人： Fumio Murabayashi ,  Takashi Hotta ,  Masahiro Iwamura ,  Akiyoshi Osumi

发明人： Fumio Murabayashi ,  Takashi Hotta ,  Masahiro Iwamura ,  Akiyoshi Osumi

IPC分类号： H03K19/013 ,  H03K19/0175 ,  H03K19/018 ,  G11C8/00 ,  H01L27/06

CPC分类号： H03K19/013 ,  H03K19/017518 ,  H03K19/01806

摘要： A semiconductor integrated circuit device is arranged to have a plurality of logic circuit blocks, a data signal path for interconnecting logic circuit blocks and for providing a function of interfacing a current-driven signal. The logic circuit block on a signal output side includes an output circuit connected to the data signal path and a switching element formed of an NMOS transistor for controlling current flowing through the data signal path in response to an input signal applied to an input terminal of the output circuit. The logic circuit block on a signal input side includes an input circuit connected to the data signal path. The input circuit includes a bipolar transistor having an emitter connected to a constant current source, a collector forming an output terminal, and a base set at a fixed potential. The data signal path led from the output circuit is connected to the emitter of the bipolar transistor. The arrangement results in reducing a signal amplitude on the signal bus, thereby speeding up the transmission of the data signal and reducing noise of the signal.

摘要翻译： 半导体集成电路器件被布置为具有多个逻辑电路块，用于互连逻辑电路块的数据信号路径，并且用于提供与电流驱动信号接口的功能。 信号输出侧的逻辑电路块包括连接到数据信号路径的输出电路和由NMOS晶体管形成的开关元件，用于响应于施加到数据信号路径的输入端子的输入信号来控制流过数据信号路径的电流 输出电路。 信号输入侧的逻辑电路块包括连接到数据信号路径的输入电路。 输入电路包括具有连接到恒流源的发射极，形成输出端的集电极和固定电位的基极的双极晶体管。 从输出电路引出的数据信号路径连接到双极晶体管的发射极。 该结构可以减少信号总线上的信号幅度，从而加速数据信号的传输并降低信号的噪声。

公开(公告)号：US20070233959A1

公开(公告)日：2007-10-04

申请号：US11802944

申请日：2007-05-29

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

公开(公告)号：US20050102472A1

公开(公告)日：2005-05-12

申请号：US11014885

申请日：2004-12-20

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

公开(公告)号：US06848027B2

公开(公告)日：2005-01-25

申请号：US10426828

申请日：2003-05-01

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

摘要翻译： 数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。 经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。 高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。 基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

公开(公告)号：US06587927B2

公开(公告)日：2003-07-01

申请号：US09864287

申请日：2001-05-25

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F1208

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

公开(公告)号：US5848432A

公开(公告)日：1998-12-08

申请号：US281002

申请日：1994-07-27

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

摘要翻译： 数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。 经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。 高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。 基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

公开(公告)号：US07240159B2

公开(公告)日：2007-07-03

申请号：US11014885

申请日：2004-12-20

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/02

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

摘要翻译： 数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。 经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。 高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。 基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

公开(公告)号：US20060152348A1

公开(公告)日：2006-07-13

申请号：US10542282

申请日：2004-11-04

申请人： Kiyokazu Ohtaki ,  Toru Maeda ,  Hisashi Kato ,  Akiyoshi Osumi ,  Takeshi Kumazaki ,  Ifushi Shimonomoto ,  Toshio Shimomura ,  Yoshinori Fukuoka ,  Koichi Masamura

发明人： Kiyokazu Ohtaki ,  Toru Maeda ,  Hisashi Kato ,  Akiyoshi Osumi ,  Takeshi Kumazaki ,  Ifushi Shimonomoto ,  Toshio Shimomura ,  Yoshinori Fukuoka ,  Koichi Masamura

IPC分类号： B60R25/10

CPC分类号： B60R25/24 ,  B60R25/04

摘要： A vehicle security device for improving the security level of a vehicle. The vehicle security device is connected to an engine and communicates with a portable device. A smart ECU performs a first coded communication to establish mutual authentication with the portable device. An ID code box is connected to the smart ECU, has a first code and a second code, and does not communicate with the portable device. The ID code box performs a second coded communication using the first code to establish a second mutual authentication with the smart ECU. An engine ECU performs a third coded communication using the second code to establish a third mutual authentication with the ID code box. The engine ECU enables the engine to be started when every one of the first, second, and third mutual authentications are established.

摘要翻译： 一种用于改善车辆安全级别的车辆安全装置。 车辆安全装置连接到发动机并与便携式装置通信。 智能ECU执行第一编码通信以建立与便携式设备的相互认证。 ID代码框连接到智能ECU，具有第一代码和第二代码，并且不与便携式设备通信。 ID代码框使用第一代码执行第二编码通信，以与智能ECU建立第二相互认证。 发动机ECU使用第二代码执行第三编码通信，以与ID代码框建立第三相互认证。 当建立第一，第二和第三相互认证中的每一个时，发动机ECU使发动机能够启动。