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    Non-restoring fixed-point divider apparatus
    1.
    发明授权
    Non-restoring fixed-point divider apparatus 失效
    非恢复定点分频器

    公开(公告)号：US5673215A

    公开(公告)日：1997-09-30

    申请号：US746708

    申请日：1996-11-15

    申请人： Albert Suan-Wei Tsay

    发明人： Albert Suan-Wei Tsay

    IPC分类号： G06F7/537 ,  G06F7/52 ,  G06F7/535

    CPC分类号： G06F7/535 ,  G06F2207/5352

    摘要： A divider for use in a data processing system and method of operation is disclosed The divider apparatus includes three 67-bit adders, coupled in parallel with one another for performing add or subtract functions, each adder being precharged during a first clock phase and executing selected functions during a second clock phase, which both occur during a single clock cycle. The first adder is connected to a first and second multiplexor, for selecting respective first and second operands. A third multiplexor, coupled to the second adder, is used to select a first operand for the second adder. Fourth and fifth multiplexors, which are coupled to the third adder, are used to select a respective first and second operand for the third adder. An adder operand select logic is coupled to the adders and the multiplexors for selecting whether to perform the add or subtract functions and for selecting which operands the multiplexors are to feed to their respective adders. An operand selection circuit is further added, which is coupled to the multiplexors and the adder operand select logic. The divider apparatus further comprising a remain quotient determination circuit coupled to the adders, and used for determining when a divide operation has been completed, what the divide result is, and whether there is a remainder quotient.

    摘要翻译： 公开了一种用于数据处理系统和操作方法的分频器。分频器包括三个67位加法器，它们彼此并联耦合，用于执行加法或减法运算，每个加法器在第一个时钟相位期间被预充电并执行选定的 在第二个时钟周期期间，它们都发生在单个时钟周期内。 第一加法器连接到第一和第二多路复用器，用于选择相应的第一和第二操作数。 耦合到第二加法器的第三多路复用器用于选择第二加法器的第一操作数。 耦合到第三加法器的第四和第五多路复用器用于为第三加法器选择相应的第一和第二操作数。 加法器操作数选择逻辑耦合到加法器和多路复用器，用于选择是执行加法还是减法函数，以及选择哪些操作数多路复用器要馈送到各自的加法器。 还添加了操作数选择电路，其被耦合到多路复用器和加法器操作数选择逻辑。 分频器装置还包括耦合到加法器的保持商确定电路，并用于确定何时分割操作已经完成，分割结果是什么，以及是否存在余数。