公开(公告)号：US06597363B1

公开(公告)日：2003-07-22

申请号：US09378637

申请日：1999-08-20

申请人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  Joseph P. Bratt ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Zhaoyu Gong ,  Thomas Y. Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew N. Papakipos ,  Jason R. Redgrave ,  Sushma S. Trivedi ,  Nathan D. Tuck

发明人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  Joseph P. Bratt ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Zhaoyu Gong ,  Thomas Y. Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew N. Papakipos ,  Jason R. Redgrave ,  Sushma S. Trivedi ,  Nathan D. Tuck

IPC分类号： G06T120

CPC分类号： G06T15/30 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/20 ,  G06T15/405 ,  G06T15/50 ,  G06T15/83

摘要： Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.

摘要翻译： 描述了包括许多子结构的图形处理器和方法，包括专用子系统，子处理器，设备，架构和相应的过程。 本发明的实施例可以包括延迟着色，出血帧缓冲器和多级隐藏表面去除处理以及其他结构和/或程序中的一个或多个。 本发明的实施例被设计为提供具有Phong着色，子像素抗锯齿，纹理和凹凸映射的高性能3D图形。

公开(公告)号：US06577305B1

公开(公告)日：2003-06-10

申请号：US09378598

申请日：1999-08-20

申请人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Hengwei Hsu ,  Sushma S. Trivedi

发明人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Hengwei Hsu ,  Sushma S. Trivedi

IPC分类号： G06T1700

CPC分类号： G06T15/20 ,  G06T1/60 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/30 ,  G06T15/40 ,  G06T15/50 ,  G06T15/80 ,  G06T15/83 ,  G06T15/87

摘要： The present invention provides post tile sorting setup in a tiled graphics pipeline architecture. In particular, the present invention determines a set of clipping points that identify intersections of a primitive with a tile. The mid-pipeline setup unit is adapted to compute a minimum depth value for that part of the primitive intersecting the tile. The mid-pipeline setup unit can be adapted to process primitives with x-coordinates that are screen based and y-coordinates that are tile based. Additionally, to the mid-pipeline setup unit is adapted to represent both line segments and triangles as quadrilaterals, wherein not all of a quadrilateral's vertices are required to describe a triangle.

摘要翻译： 本发明提供了一种平铺图形流水线架构中的贴砖排序设置。 特别地，本发明确定了识别原始图像与瓦片的交叉点的一组剪切点。 中间管道设置单元适于计算与瓦片相交的原始部分的最小深度值。 中间流水线设置单元可以适用于处理基于屏幕的x坐标的基元和基于瓦片的y坐标。 另外，中间流水线设置单元适于将线段和三角形表示为四边形，其中不需要全部四边形的顶点来描述三角形。

公开(公告)号：US5272453A

公开(公告)日：1993-12-21

申请号：US923767

申请日：1992-08-03

申请人： Kevin M. Traynor ,  Hengwei Hsu ,  Kenneth R. Burch

发明人： Kevin M. Traynor ,  Hengwei Hsu ,  Kenneth R. Burch

IPC分类号： H03K3/03 ,  H03L7/089 ,  H03L7/099 ,  H03L7/14 ,  H03B5/02

CPC分类号： H03K3/0315 ,  H03L7/0995 ,  H03L7/14 ,  H03L2207/06 ,  H03L7/0891

摘要： A method and apparatus for switching between gain curves of a switched gain voltage controlled oscillator (VCO) 52, 52' or 52". In one form, the present invention uses a switched gain voltage controlled oscillator (VCO) 52, 52' or 52" which utilizes a ring oscillator. A Gain Control signal is used to select between using a high gain curve and using a low gain curve. The low gain curve is produced by selecting a high resistance path to either power or ground. The high gain curve is produced by selecting a low resistance path to either power or ground.

摘要翻译： 一种用于切换开关增益压控振荡器（VCO）52,52'或52“的增益曲线之间切换的方法和装置。 在一种形式中，本发明使用利用环形振荡器的开关增益压控振荡器（VCO）52,52'或52“。 增益控制信号用于在使用高增益曲线和使用低增益曲线之间进行选择。 低增益曲线是通过选择电源或接地的高电阻路径产生的。 通过选择电源或接地的低电阻路径来产生高增益曲线。

公开(公告)号：US07808503B2

公开(公告)日：2010-10-05

申请号：US11613093

申请日：2006-12-19

申请人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  Joseph P. Bratt ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Zhaoyu Gong ,  Thomas Y. Yo ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew N. Papakipos ,  Jason R. Redgrave ,  Sushma S. Trivedi ,  Nathan D. Tuck ,  Shun Wai Go ,  Lindy Fung ,  Tuan D. Nguyen ,  Joseph P. Grass ,  Bo Hong ,  Abraham Mammen ,  Abbas Rashid ,  Albert Suan-Wei Tsay

发明人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  Joseph P. Bratt ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Zhaoyu Gong ,  Thomas Y. Yo ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew N. Papakipos ,  Jason R. Redgrave ,  Sushma S. Trivedi ,  Nathan D. Tuck ,  Shun Wai Go ,  Lindy Fung ,  Tuan D. Nguyen ,  Joseph P. Grass ,  Bo Hong ,  Abraham Mammen ,  Abbas Rashid ,  Albert Suan-Wei Tsay

IPC分类号： G06T1/20 ,  G06T15/00 ,  G06T15/10

CPC分类号： G06T15/20 ,  G06T1/60 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/30 ,  G06T15/40 ,  G06T15/50 ,  G06T15/80 ,  G06T15/83 ,  G06T15/87

摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

摘要翻译： 提供了包括许多子结构的延迟着色图形流水线处理器和方法。 处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。 在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。 流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元， 像素单元和后端单元。

公开(公告)号：US06717576B1

公开(公告)日：2004-04-06

申请号：US09377503

申请日：1999-08-20

申请人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  Joseph P. Bratt ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Zhaoyu Gong ,  Thomas Y. Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew N. Papakipos ,  Jason R. Redgrave ,  Sushma S. Trivedi ,  Nathan D. Tuck ,  Shun Wai Go ,  Lindy Fung ,  Tuan D. Nguyen ,  Joseph P. Grass ,  Bo Hong ,  Abraham Mammen ,  Abbas Rashid ,  Albert Suan-Wei Tsay

发明人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  Joseph P. Bratt ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Zhaoyu Gong ,  Thomas Y. Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew N. Papakipos ,  Jason R. Redgrave ,  Sushma S. Trivedi ,  Nathan D. Tuck ,  Shun Wai Go ,  Lindy Fung ,  Tuan D. Nguyen ,  Joseph P. Grass ,  Bo Hong ,  Abraham Mammen ,  Abbas Rashid ,  Albert Suan-Wei Tsay

IPC分类号： G06T1500

CPC分类号： G06T15/30 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/20 ,  G06T15/405 ,  G06T15/50 ,  G06T15/83

摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

摘要翻译： 提供了包括许多子结构的延迟着色图形流水线处理器和方法。 处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。 在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。 流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元， 像素单元和后端单元。

公开(公告)号：US06664959B2

公开(公告)日：2003-12-16

申请号：US10231436

申请日：2002-08-29

申请人： Jerome F. Duluk, Jr. ,  Stephen L. Dodgen ,  Richard E. Hessel ,  Emerson S. Fang ,  Hengwei Hsu ,  Jason R. Redgrave ,  Sushma S. Trivedi

发明人： Jerome F. Duluk, Jr. ,  Stephen L. Dodgen ,  Richard E. Hessel ,  Emerson S. Fang ,  Hengwei Hsu ,  Jason R. Redgrave ,  Sushma S. Trivedi

IPC分类号： G06T1540

CPC分类号： G06T15/20 ,  G06T1/60 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/30 ,  G06T15/40 ,  G06T15/50 ,  G06T15/80 ,  G06T15/83 ,  G06T15/87

摘要： Structure, apparatus, and method for performing conservative hidden surface removal in a graphics processor. Culling is divided into two steps, a magnitude comparison content addressable memory cull operation (MCCAM Cull), and a subpixel cull operation. The MCCAM Cull discards primitives that are hidden completely by previously processed geometry. The Subpixel Cull takes the remaining primitives (which are partly or entirely visible), and determines the visible fragments. In one embodiment the method of performing hidden surface removal includes: selecting a current primitive comprising a plurality of stamps; comparing stamps to stamps from previously evaluated primitives; selecting a first stamp as a currently potentially visible stamp (CPVS) based on a relationship of depth states of samples in the first stamp with depth states of samples of previously evaluated stamps; comparing the CPVS to a second stamp; discarding the second stamp when no part of the second stamp would affect a final graphics display image based on the stamps that have been evaluated; discarding the CPVS and making the second stamp the CPVS, when the second stamp hides the CPVS; dispatching the CPVS and making the second stamp the CPVS when both the second stamp and the CPVS are at least partially visible in the final graphics display image; and dispatching the second stamp and the CPVS when the visibility of the second stamp and the CPVS depends on parameters evaluated later in the computer graphics pipeline.

公开(公告)号：US06476807B1

公开(公告)日：2002-11-05

申请号：US09378391

申请日：1999-08-20

申请人： Jerome F. Duluk, Jr. ,  Stephen L. Dodgen ,  Richard E. Hessel ,  Emerson S. Fang ,  Hengwei Hsu ,  Jason R. Redgrave ,  Sushma S. Trivedi

发明人： Jerome F. Duluk, Jr. ,  Stephen L. Dodgen ,  Richard E. Hessel ,  Emerson S. Fang ,  Hengwei Hsu ,  Jason R. Redgrave ,  Sushma S. Trivedi

IPC分类号： G06T1540

CPC分类号： G06T15/20 ,  G06T1/60 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/30 ,  G06T15/40 ,  G06T15/50 ,  G06T15/80 ,  G06T15/83 ,  G06T15/87

摘要： Structure, apparatus, and method for performing conservative hidden surface removal in a graphics processor. Culling is divided into two steps, a magnitude comparison content addressable memory cull operation (MCCAM Cull), and a subpixel cull operation. The MCCAM Cull discards primitives that are hidden completely by previously processed geometry. The Subpixel Cull takes the remaining primitives (which are partly or entirely visible), and determines the visible fragments. In one embodiment the method of performing hidden surface removal includes: selecting a current primitive comprising a plurality of stamps; comparing stamps to stamps from previously evaluated primitives; selecting a first stamp as a currently potentially visible stamp (CPVS) based on a relationship of depth states of samples in the first stamp with depth states of samples of previously evaluated stamps; comparing the CPVS to a second stamp; discarding the second stamp when no part of the second stamp would affect a final graphics display image based on the stamps that have been evaluated; discarding the CPVS and making the second stamp the CPVS, when the second stamp hides the CPVS; dispatching the CPVS and making the second stamp the CPVS when both the second stamp and the CPVS are at least partially visible in the final graphics display image; and dispatching the second stamp and the CPVS when the visibility of the second stamp and the CPVS depends on parameters evaluated later in the computer graphics pipeline.

摘要翻译： 用于在图形处理器中执行保守的隐藏表面去除的结构，装置和方法。 剔除分为两个步骤，幅度比较内容可寻址存储器剔除操作（MCCAM Cull）和子像素剔除操作。 MCCAM Cull将丢弃由先前处理过的几何完全隐藏的原语。 子像素Cull获取剩余的基元（部分或全部可见），并确定可见碎片。 在一个实施例中，执行隐藏表面去除的方法包括：选择包括多个邮票的当前图元; 将邮票与先前评估的图案的邮票进行比较; 基于所述第一印记中的样本的深度状态与先前评估的标记的样本的深度状态的关系，选择第一印记作为当前潜在可见印记（CPVS）; 将CPVS与第二个邮票进行比较; 当第二印章的任何部分都不会影响基于所评估的邮票的最终图形显示图像时，丢弃第二印记; 丢弃CPVS，并将第二个邮票隐藏CPVS; 在最终图形显示图像中至少部分地可见第二印记和CPVS时，分派CPVS并使第二印记CPVS; 并且当第二印章和CPVS的可视性取决于计算机图形管线中稍后评估的参数时，分派第二印记和CPVS。

公开(公告)号：US06268875B1

公开(公告)日：2001-07-31

申请号：US09632293

申请日：2000-08-04

申请人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  Joseph P. Bratt ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Zhaoyu Gong ,  Thomas Y. Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew N. Papakipos ,  Jason R. Redgrave ,  Sushma S. Trivedi ,  Nathan D. Tuck

发明人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  Joseph P. Bratt ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Zhaoyu Gong ,  Thomas Y. Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew N. Papakipos ,  Jason R. Redgrave ,  Sushma S. Trivedi ,  Nathan D. Tuck

IPC分类号： G06T120

CPC分类号： G06T15/20 ,  G06T1/60 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/30 ,  G06T15/40 ,  G06T15/50 ,  G06T15/80 ,  G06T15/83 ,  G06T15/87

摘要： Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch & decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000) a phong shading (14000), a pixel unit (15000), a backend unit (1600) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

摘要翻译： 三维计算机图形系统和方法，更具体地涉及三维图形处理器的结构和方法，并具有其他增强的图形处理特征。 在一个实施例中，图形处理器是包括AGP接口，命令提取和解码（2000），几何单元（3000），模式提取（4000）和多边形存储器（5000）的延迟着色图形处理器（DSGP） 分类单元（6000）和分类存储器（7000），设置单元（8000），剔除单元（9000），模式注入（10000），片段单元（11000），纹理（12000）和纹理存储器 ）阴影（14000），像素单元（15000），耦合到帧缓冲器（17000）的后端单元（1600）。 其他实施例不需要包括所有这些功能单元，并且这些单元的结构和方法适用于其他计算过程和系统以及延迟和非延迟着色图形处理器。

公开(公告)号：US20070165035A1

公开(公告)日：2007-07-19

申请号：US11613093

申请日：2006-12-19

申请人： Jerome Duluk ,  Richard Hessel ,  Vaughn Arnold ,  Jack Benkual ,  Joseph Bratt ,  George Cuan ,  Stephen Dodgen ,  Emerson Fang ,  Zhaoyu Gong ,  Thomas Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew Papakipos ,  Jason Redgrave ,  Sushma Trivedi ,  Nathan Tuck ,  Shun Go ,  Lindy Fung ,  Tuan Nguyen ,  Joseph Grass ,  Bo Hung ,  Abraham Mammen ,  Abbas Rashid ,  Albert Tsay

发明人： Jerome Duluk ,  Richard Hessel ,  Vaughn Arnold ,  Jack Benkual ,  Joseph Bratt ,  George Cuan ,  Stephen Dodgen ,  Emerson Fang ,  Zhaoyu Gong ,  Thomas Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew Papakipos ,  Jason Redgrave ,  Sushma Trivedi ,  Nathan Tuck ,  Shun Go ,  Lindy Fung ,  Tuan Nguyen ,  Joseph Grass ,  Bo Hung ,  Abraham Mammen ,  Abbas Rashid ,  Albert Tsay

IPC分类号： G06T1/20

CPC分类号： G06T15/20 ,  G06T1/60 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/30 ,  G06T15/40 ,  G06T15/50 ,  G06T15/80 ,  G06T15/83 ,  G06T15/87

摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

摘要翻译： 提供了包括许多子结构的延迟着色图形流水线处理器和方法。 处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。 在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。 流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元， 像素单元和后端单元。

公开(公告)号：US07167181B2

公开(公告)日：2007-01-23

申请号：US10458493

申请日：2003-06-09

申请人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  Joseph P. Bratt ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Zhaoyu Gong ,  Thomas Y. Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew N. Papakipos ,  Jason R. Redgrave ,  Sushma S. Trivedi ,  Nathan D. Tuck ,  Shun Wai Go ,  Lindy Fung ,  Tuan D. Nguyen ,  Joseph P. Grass ,  Bo Hong ,  Abraham Mammen ,  Abbas Rashid ,  Albert Suan-Wei Tsay

发明人： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Vaughn T. Arnold ,  Jack Benkual ,  Joseph P. Bratt ,  George Cuan ,  Stephen L. Dodgen ,  Emerson S. Fang ,  Zhaoyu Gong ,  Thomas Y. Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew N. Papakipos ,  Jason R. Redgrave ,  Sushma S. Trivedi ,  Nathan D. Tuck ,  Shun Wai Go ,  Lindy Fung ,  Tuan D. Nguyen ,  Joseph P. Grass ,  Bo Hong ,  Abraham Mammen ,  Abbas Rashid ,  Albert Suan-Wei Tsay

IPC分类号： G06T1/20 ,  G06T15/40 ,  G09G5/00

CPC分类号： G06T15/30 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/20 ,  G06T15/405 ,  G06T15/50 ,  G06T15/83

摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

摘要翻译： 提供了包括许多子结构的延迟着色图形流水线处理器和方法。 处理器和方法的实施例可以包括延迟着色，平铺的帧缓冲器和多个阶段隐藏表面去除处理中的一个或多个。 在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。 流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元， 像素单元和后端单元。