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公开(公告)号：US07412017B2
公开(公告)日：2008-08-12
申请号：US11931962
申请日：2007-10-31
IPC分类号： H04L7/00
CPC分类号： H04L7/0054 , H04L7/0338
摘要： An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases and then picks a sample sequence that allows for the most reliable detection. For the different sampling phases, the detector inspects some amount of look-behind and look-ahead information in order to improve upon simple symbol-by-symbol detection. The over-sampled information is used to further improve detection performance.
摘要翻译： 过采样序列检测器对采样数据进行操作，并跟踪采样数据的检测可靠性。 检测器单独分析不同采样阶段的样品序列，然后选择一个允许最可靠检测的样品序列。 对于不同的采样阶段，检测器检查一些量的前瞻和预先信息，以便改进简单的符号符号检测。 过采样信息用于进一步提高检测性能。
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2.发明授权Monolithic integrated circuit implemented in a digital display unit for generating digital data elements from an analog display signal received at high frequencies 有权实现在数字显示单元中用于从高频接收的模拟显示信号产生数字数据元素的单片集成电路公开(公告)号：US06459426B1
公开(公告)日：2002-10-01
申请号：US09135216
申请日：1998-08-17
IPC分类号： H03M112
CPC分类号： B60R25/102 , B60R25/1018 , B60R25/2009 , B60R2325/304 , B60R2325/306 , B62H5/00 , B62H5/20
摘要： A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.
摘要翻译： 一种用于数字显示单元的单片集成电路。 电路可以包括模数转换器（ADC），缩放器和时钟恢复电路。 本发明使得至少将这些组件集成到单个单片集成电路中同时保持合理的显示质量。 具体地，单片集成电路被设计用于实质上抗噪声的抗扰性，否则这可能由集成引起。
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3.发明授权Method and apparatus implemented in an automatic sampling phase control system for digital monitors 有权在数字监视器的自动采样相位控制系统中实现的方法和装置公开(公告)号：US06268848B1
公开(公告)日：2001-07-31
申请号：US09177897
申请日：1998-10-23
IPC分类号： G09G500
摘要： An automatic sampling control system for digital monitors. A clock generation circuit generates a sampling clock. A phase controller modifies the phase of the sampling clock by a phase amount. An ADC samples a frame of an analog display signal to generate digital samples. A value which is a function of the samples is generated. The function generally generates a larger value with correspondingly large sample values. The phase amount is modified for successive image frames until a maximum function value is generated. When successive image frames do not change substantially in image content, the phase amount represents the optimal phase change for the sampling clock. If the image content is changing substantially, the phase adjustment may be disabled.
摘要翻译： 一种用于数字显示器的自动采样控制系统。 时钟发生电路产生采样时钟。 相位控制器将采样时钟的相位修改相位量。 ADC对模拟显示信号的帧进行采样以产生数字采样。 生成作为样本的函数的值。 该函数通常产生较大的值，并具有相应较大的样本值。 对于连续的图像帧修改相位量，直到产生最大函数值。 当连续的图像帧在图像内容中基本不变化时，相位量表示采样时钟的最佳相位变化。 如果图像内容显着变化，则可以禁用相位调整。
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4.发明授权Digital display unit in a computer system with an improved method and apparatus for determining a source mode using which a received analog display signal was generated 失效具有改进的方法和装置的计算机系统中的数字显示单元，用于确定产生接收的模拟显示信号的源模式
公开(公告)号：US6028571A
公开(公告)日：2000-02-22
申请号：US35261
申请日：1998-03-05
CPC分类号： G09G5/006
摘要： A digital display unit which accurately determines a graphics source mode using which an analog display signal has been generated. Accurate determination of the source mode enables images encoded in the received display signal to be reproduced properly on a digital display screen. Some of the display signal parameters are measured by examining the display signal. The measured parameters are compared with corresponding stored parameters for each stored mode. A match of parameters is deemed to exist if the compared values are within an associated tolerance level. A source mode matching with all matching parameter is selected to process a display signal. The tolerance level is adaptively varied to select a suitable source mode.
摘要翻译： 一种数字显示单元，其准确地确定已经生成模拟显示信号的图形源模式。 准确地确定源模式使得在数字显示屏上正确地再现所接收的显示信号中编码的图像。 通过检查显示信号来测量一些显示信号参数。 将测量的参数与每个存储模式的相应存储参数进行比较。 如果比较值在相关的公差水平内，则认为参数匹配存在。 选择与所有匹配参数匹配的源模式来处理显示信号。 自适应地改变公差水平以选择合适的源模式。
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5.发明授权Method and apparatus for upscaling video images when pixel data used for upscaling a source video image are unavailable 失效当用于升级源视频图像的像素数据不可用时，用于放大视频图像的方法和装置
公开(公告)号：US5703618A
公开(公告)日：1997-12-30
申请号：US561907
申请日：1995-11-22
CPC分类号： G06T3/4007
摘要： A graphics controller circuit for upscaling source video image to generate an upscaled video image. The graphics controller circuit generates additional pixel data for the upscaled video image by interpolating source video pixel data of a one scan line and an another scan line. However, when source video pixel data of the another scan line may not be available for interpolation, the graphics controller circuit generates additional pixel data from source video pixel data of only the one scan line. Source video pixel data of the another scan line may not be available, for example, as a bus that transfers the pixel data may not have sufficient amount of bandwidth.
摘要翻译： 一种用于升级源视频图像以生成放大的视频图像的图形控制器电路。 图形控制器电路通过内插一条扫描线和另一条扫描线的源视频像素数据来产生用于放大的视频图像的附加像素数据。 然而，当另一扫描线的源视频像素数据可能不可用于插值时，图形控制器电路从仅一条扫描线的源视频像素数据生成附加像素数据。 另一条扫描线的源视频像素数据可能不可用，例如，传输像素数据的总线可能没有足够的带宽量。
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6.发明授权公开(公告)号：US07292665B2
公开(公告)日：2007-11-06
申请号：US11069194
申请日：2005-02-28
IPC分类号： H04L7/00
CPC分类号： H04L7/0054 , H04L7/0338
摘要： An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases and then picks a sample sequence that allows for the most reliable detection. For the different sampling phases, the detector inspects some amount of look-behind and look-ahead information in order to improve upon simple symbol-by-symbol detection. The over-sampled information is used to further improve detection performance.
摘要翻译： 过采样序列检测器对采样数据进行操作，并跟踪采样数据的检测可靠性。 检测器单独分析不同采样阶段的样品序列，然后选择一个允许最可靠检测的样品序列。 对于不同的采样阶段，检测器检查一些量的前瞻和预先信息，以便改进简单的符号符号检测。 过采样信息用于进一步提高检测性能。
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7.发明授权Digital display unit which adjusts the sampling phase dynamically for accurate recovery of pixel data encoded in an analog display signal 有权数字显示单元，其动态地调整采样相位，以精确恢复以模拟显示信号编码的像素数据公开(公告)号：US06483447B1
公开(公告)日：2002-11-19
申请号：US09350204
申请日：1999-07-07
IPC分类号： H03M148
摘要： A digital display unit adjusting the phase of a sampling clock based on the examination of a display data signal contained in a received analog display signal. The phase may be adjusted by determining a boundary between display data portions representing successive pixel data elements. As the boundaries provide the timing information related to the source clock, the phase of the sampling clock can be adjusted when ever the boundaries can be determined accurately. The phase of the sampling clock can be adjusted potentially every sampling clock cycle if the boundaries can be determined. The area for examination can be minimized by first determining an expected boundary based on synchronization signal accompanying the analog display data, and examining only a small area surrounding the expected boundary.
摘要翻译： 数字显示单元，其基于对接收的模拟显示信号中包含的显示数据信号的检查来调整采样时钟的相位。 可以通过确定表示连续的像素数据元素的显示数据部分之间的边界来调整相位。 由于边界提供与源时钟相关的定时信息，因此当可以准确地确定边界时，可以调整采样时钟的相位。 如果可以确定边界，则采样时钟的相位可以在每个采样时钟周期进行调整。 可以通过首先根据伴随模拟显示数据的同步信号确定预期边界，并仅检查围绕预期边界的小区域，来最小化检查区域。
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公开(公告)号：US6118413A
公开(公告)日：2000-09-12
申请号：US136791
申请日：1998-08-19
申请人： Vlad Bril , Rakesh Bindlish , Ken Fuiks , Robin Sungsoo Han , Sridhar Kotha , Alexander Julian Eglit
发明人： Vlad Bril , Rakesh Bindlish , Ken Fuiks , Robin Sungsoo Han , Sridhar Kotha , Alexander Julian Eglit
CPC分类号： G06F3/1431 , G09G2360/04 , G09G3/2051 , G09G5/39 , G09G5/395
摘要： A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g., LCD and CRT) are provided to temporarily store video data. FIFO pointers are fed back to a sequence controller to drive data read cycles from display memory. The use of tags and FIFO pointer feedback allows two video displays to be driven at different data rates, allowing for independent resolution and refresh rates in each display.
摘要翻译： 一种用于控制具有独立的刷新率和像素分辨率的至少两个视频显示器的视频控制器。 在第一实施例中，在每个视频显示器（例如CRT和LCD）的视频控制器内提供两个单独的数据路径。 利用64位宽的DRAMS的带宽增加，可以在单独的读取周期中检索每个数据路径的数据。 每个数据通路可以在其自己的时钟频率下操作刷新率和像素分辨率的特性。 双数据路径实施例还降低了驱动这种双显示器所需的软件模型的复杂性。 在替代实施例中，可以在视频控制器内提供单个数据路径来驱动具有独立刷新率和像素分辨率的两个视频显示器的数据。 附加到通过指示视频数据的目的地（例如，CRT或LCD）的数据路径的每个字或双字的数据“标签”（额外位）。 在数据路径的输出端，提供分离的FIFO（例如LCD和CRT）以临时存储视频数据。 FIFO指针被反馈到序列控制器以从显示存储器驱动数据读取周期。 使用标签和FIFO指针反馈允许以不同的数据速率驱动两个视频显示器，允许在每个显示器中独立分辨率和刷新率。
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9.发明授权Method and apparatus for automatically determining signal parameters of an analog display signal received by a display unit of a computer system 失效用于自动确定由计算机系统的显示单元接收的模拟显示信号的信号参数的方法和装置
公开(公告)号：US5987624A
公开(公告)日：1999-11-16
申请号：US872764
申请日：1997-06-10
CPC分类号： G09G5/006 , G09G2320/0606 , G09G2320/0673 , G09G2320/0693
摘要： A computer system in which the signal parameters of an analog display signal received by a display unit can be determined automatically. A test data having a predetermined format is sent to a display unit. The test data is encoded to enable display unit to measure display signal parameters such as the timing signals (e.g., start position of each horizontal line) accurately. The test data also includes black and white points, which enable the display unit to measure the voltage levels used to represent black and white signals. Display unit can accordingly adjust the manner in which individual points on a display screen are actuated so that the full scale of brightness levels on individual points can be utilized. CRC-based techniques are used to indicate to the display unit the presence of the test data as the same communication path is used to send test data and display data.
摘要翻译： 可以自动确定由显示单元接收的模拟显示信号的信号参数的计算机系统。 具有预定格式的测试数据被发送到显示单元。 对测试数据进行编码，以使显示单元精确地测量诸如定时信号（例如每条水平行的开始位置）的显示信号参数。 测试数据还包括黑点和白点，使显示单元能够测量用于表示黑白信号的电压电平。 因此，显示单元可以相应地调整显示屏幕上的各点被致动的方式，使得可以利用各个点上的亮度级别的满刻度。 基于CRC的技术用于向显示单元指示测试数据的存在，因为相同的通信路径用于发送测试数据和显示数据。
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公开(公告)号：US5818405A
公开(公告)日：1998-10-06
申请号：US555991
申请日：1995-11-15
CPC分类号： G09G3/2003 , G09G2320/0247 , G09G2330/025 , G09G3/2025 , G09G3/2051
摘要： An apparatus for controlling a flat panel display with reduced flicker, particularly during grey scale shading. Three shading pattern lookup tables are provided, one for each sub-pixel color (Red, Blue, Green). Each shading pattern lookup table outputs a plurality of shading pattern duty cycle signals, each representing a different shade level. The phase of the three duty cycle signal patterns may be altered by adding a predetermined offset amount to one or more of the shading pattern lookup table addresses. By altering the phases of the outputs of the shading lookup tables, peak current demand within the flat panel display may be reduced and flicker or strobing of individual pixels may be reduced or eliminated.
摘要翻译： 一种用于控制平板显示器的装置，其特别是在灰度阴影下，具有减少的闪烁。 提供三个阴影图案查找表，每个子像素颜色（红，蓝，绿）一个。 每个阴影图案查找表输出多个阴影图案占空比信号，每个信号表示不同的色阶。 可以通过向阴影图案查找表地址中的一个或多个添加预定偏移量来改变三个占空比信号模式的相位。 通过改变阴影查找表的输出的相位，可以减少平板显示器内的峰值电流需求，并且可以减少或消除单个像素的闪烁或选通。
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