公开(公告)号：US6118413A

公开(公告)日：2000-09-12

申请号：US136791

申请日：1998-08-19

申请人： Vlad Bril ,  Rakesh Bindlish ,  Ken Fuiks ,  Robin Sungsoo Han ,  Sridhar Kotha ,  Alexander Julian Eglit

发明人： Vlad Bril ,  Rakesh Bindlish ,  Ken Fuiks ,  Robin Sungsoo Han ,  Sridhar Kotha ,  Alexander Julian Eglit

IPC分类号： G06F3/14 ,  G09G3/20 ,  G09G5/39 ,  G09G5/395 ,  G09G5/00

CPC分类号： G06F3/1431 ,  G09G2360/04 ,  G09G3/2051 ,  G09G5/39 ,  G09G5/395

摘要： A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g., LCD and CRT) are provided to temporarily store video data. FIFO pointers are fed back to a sequence controller to drive data read cycles from display memory. The use of tags and FIFO pointer feedback allows two video displays to be driven at different data rates, allowing for independent resolution and refresh rates in each display.

摘要翻译： 一种用于控制具有独立的刷新率和像素分辨率的至少两个视频显示器的视频控制器。 在第一实施例中，在每个视频显示器（例如CRT和LCD）的视频控制器内提供两个单独的数据路径。 利用64位宽的DRAMS的带宽增加，可以在单独的读取周期中检索每个数据路径的数据。 每个数据通路可以在其自己的时钟频率下操作刷新率和像素分辨率的特性。 双数据路径实施例还降低了驱动这种双显示器所需的软件模型的复杂性。 在替代实施例中，可以在视频控制器内提供单个数据路径来驱动具有独立刷新率和像素分辨率的两个视频显示器的数据。 附加到通过指示视频数据的目的地（例如，CRT或LCD）的数据路径的每个字或双字的数据“标签”（额外位）。 在数据路径的输出端，提供分离的FIFO（例如LCD和CRT）以临时存储视频数据。 FIFO指针被反馈到序列控制器以从显示存储器驱动数据读取周期。 使用标签和FIFO指针反馈允许以不同的数据速率驱动两个视频显示器，允许在每个显示器中独立分辨率和刷新率。

公开(公告)号：US5841418A

公开(公告)日：1998-11-24

申请号：US483584

申请日：1995-06-07

申请人： Vald Bril ,  Rakesh Bindlish ,  Ken Fuiks ,  Robin Sungsoo Han ,  Sridhar Kotha ,  Alexander Julian Eglit

发明人： Vald Bril ,  Rakesh Bindlish ,  Ken Fuiks ,  Robin Sungsoo Han ,  Sridhar Kotha ,  Alexander Julian Eglit

IPC分类号： G06F3/14 ,  G09G3/20 ,  G09G5/39 ,  G09G5/395 ,  G09G5/00

CPC分类号： G06F3/1431 ,  G09G2360/04 ,  G09G3/2051 ,  G09G5/39 ,  G09G5/395

摘要： A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g., LCD and CRT) are provided to temporarily store video data. FIFO pointers are fed back to a sequence controller to drive data read cycles from display memory. The use of tags and FIFO pointer feedback allows two video displays to be driven at different data rates, allowing for independent resolution and refresh rates in each display.

公开(公告)号：US06310599B1

公开(公告)日：2001-10-30

申请号：US08704842

申请日：1996-08-28

申请人： Vlad Bril ,  Alexander Julian Eglit ,  Robin Sungsoo Han ,  Muralidhar Reddy Jammula

发明人： Vlad Bril ,  Alexander Julian Eglit ,  Robin Sungsoo Han ,  Muralidhar Reddy Jammula

IPC分类号： G09G333

CPC分类号： G09G3/36 ,  G09G2330/02 ,  G09G2330/04

摘要： A flat panel display controller is provided with a circuit for monitoring clocking signal(s) to the flat panel display. A clocking signal output to the flat panel display may be fed back to the display controller using a conventional I/O pad. In the preferred embodiment, the fed back clocking signal resets a counter. In a second embodiment, the fed back clocking signal may then pass through an edge detector whose output then resets the counter. The counter will overflow if a edge signal is not received within a predetermined time period. If an overflow occurs, the carry signal of the counter will initiate a flat panel power shutdown through power control circuitry. The clock signal for the counter may be derived from an off-chip oscillator such that if a failure occurs within the display controller, the counter will continue to function.

摘要翻译： 平板显示控制器设置有用于监视平板显示器的时钟信号的电路。 输出到平板显示器的定时信号可以使用传统的I / O垫反馈到显示控制器。 在优选实施例中，反馈时钟信号复位计数器。 在第二实施例中，反馈时钟信号然后可以通过边沿检测器，其输出然后复位该计数器。 如果在预定时间段内没有接收到边缘信号，计数器将溢出。 如果发生溢出，计数器的进位信号将通过电源控制电路启动平板电源关闭。 计数器的时钟信号可以从片外振荡器导出，使得如果在显示控制器内发生故障，则计数器将继续工作。

公开(公告)号：US5818405A

公开(公告)日：1998-10-06

申请号：US555991

申请日：1995-11-15

申请人： Alexander Julian Eglit ,  Robin Sungsoo Han

发明人： Alexander Julian Eglit ,  Robin Sungsoo Han

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  H04N9/12

CPC分类号： G09G3/2003 ,  G09G2320/0247 ,  G09G2330/025 ,  G09G3/2025 ,  G09G3/2051

摘要： An apparatus for controlling a flat panel display with reduced flicker, particularly during grey scale shading. Three shading pattern lookup tables are provided, one for each sub-pixel color (Red, Blue, Green). Each shading pattern lookup table outputs a plurality of shading pattern duty cycle signals, each representing a different shade level. The phase of the three duty cycle signal patterns may be altered by adding a predetermined offset amount to one or more of the shading pattern lookup table addresses. By altering the phases of the outputs of the shading lookup tables, peak current demand within the flat panel display may be reduced and flicker or strobing of individual pixels may be reduced or eliminated.

摘要翻译： 一种用于控制平板显示器的装置，其特别是在灰度阴影下，具有减少的闪烁。 提供三个阴影图案查找表，每个子像素颜色（红，蓝，绿）一个。 每个阴影图案查找表输出多个阴影图案占空比信号，每个信号表示不同的色阶。 可以通过向阴影图案查找表地址中的一个或多个添加预定偏移量来改变三个占空比信号模式的相位。 通过改变阴影查找表的输出的相位，可以减少平板显示器内的峰值电流需求，并且可以减少或消除单个像素的闪烁或选通。

公开(公告)号：US06046738A

公开(公告)日：2000-04-04

申请号：US909825

申请日：1997-08-12

申请人： Alexander Julian Eglit ,  Robin Sungsoo Han

发明人： Alexander Julian Eglit ,  Robin Sungsoo Han

IPC分类号： G09G3/20 ,  G09G5/00 ,  G09G5/30

CPC分类号： G09G5/006

摘要： A digital display unit receiving a display signal with image encoded at high origin frequencies (e.g., dot clock). A display signal interface samples the display signal during source display time to generate pixel data elements representative of the images encoded in the display signal. The signal is sampled at a sampling frequency equal to origin frequency. The pixel data elements are stored in a buffer at the sampling frequency and retrieved at a slower frequency. Display signals are generated for each horizontal scan line of a digital display screen during a destination display time at this slower frequency. The destination display time is designed to be longer than the source display time, which enables the display signals to be generated from all pixel data elements. The destination display time is longer than the source display time because digital display units do not require the long non-display times present in the display signals.

摘要翻译： 数字显示单元接收具有以高起始频率（例如点时钟）编码的图像的显示信号。 显示信号接口在源显示时间期间对显示信号进行采样，以生成表示在显示信号中编码的图像的像素数据元素。 以等于原始频率的采样频率采样信号。 像素数据元素以采样频率存储在缓冲器中并且以较慢的频率被检索。 在该较慢频率的目的地显示时间期间，为数字显示屏幕的每个水平扫描线生成显示信号。 目的地显示时间被设计为比源显示时间长，这使得能够从所有像素数据元素生成显示信号。 目的地显示时间长于源显示时间，因为数字显示单元不需要在显示信号中存在长的非显示时间。

公开(公告)号：US07412017B2

公开(公告)日：2008-08-12

申请号：US11931962

申请日：2007-10-31

申请人： Alexander Julian Eglit

发明人： Alexander Julian Eglit

IPC分类号： H04L7/00

CPC分类号： H04L7/0054 ,  H04L7/0338

摘要： An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases and then picks a sample sequence that allows for the most reliable detection. For the different sampling phases, the detector inspects some amount of look-behind and look-ahead information in order to improve upon simple symbol-by-symbol detection. The over-sampled information is used to further improve detection performance.

摘要翻译： 过采样序列检测器对采样数据进行操作，并跟踪采样数据的检测可靠性。 检测器单独分析不同采样阶段的样品序列，然后选择一个允许最可靠检测的样品序列。 对于不同的采样阶段，检测器检查一些量的前瞻和预先信息，以便改进简单的符号符号检测。 过采样信息用于进一步提高检测性能。

公开(公告)号：US06459426B1

公开(公告)日：2002-10-01

申请号：US09135216

申请日：1998-08-17

申请人： Alexander Julian Eglit ,  Tzoyao Chan ,  John Lattanzi

发明人： Alexander Julian Eglit ,  Tzoyao Chan ,  John Lattanzi

IPC分类号： H03M112

CPC分类号： B60R25/102 ,  B60R25/1018 ,  B60R25/2009 ,  B60R2325/304 ,  B60R2325/306 ,  B62H5/00 ,  B62H5/20

摘要： A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.

摘要翻译： 一种用于数字显示单元的单片集成电路。 电路可以包括模数转换器（ADC），缩放器和时钟恢复电路。 本发明使得至少将这些组件集成到单个单片集成电路中同时保持合理的显示质量。 具体地，单片集成电路被设计用于实质上抗噪声的抗扰性，否则这可能由集成引起。

公开(公告)号：US06268848B1

公开(公告)日：2001-07-31

申请号：US09177897

申请日：1998-10-23

申请人： Alexander Julian Eglit

发明人： Alexander Julian Eglit

IPC分类号： G09G500

CPC分类号： G09G5/008 ,  G09G5/006

摘要： An automatic sampling control system for digital monitors. A clock generation circuit generates a sampling clock. A phase controller modifies the phase of the sampling clock by a phase amount. An ADC samples a frame of an analog display signal to generate digital samples. A value which is a function of the samples is generated. The function generally generates a larger value with correspondingly large sample values. The phase amount is modified for successive image frames until a maximum function value is generated. When successive image frames do not change substantially in image content, the phase amount represents the optimal phase change for the sampling clock. If the image content is changing substantially, the phase adjustment may be disabled.

摘要翻译： 一种用于数字显示器的自动采样控制系统。 时钟发生电路产生采样时钟。 相位控制器将采样时钟的相位修改相位量。 ADC对模拟显示信号的帧进行采样以产生数字采样。 生成作为样本的函数的值。 该函数通常产生较大的值，并具有相应较大的样本值。 对于连续的图像帧修改相位量，直到产生最大函数值。 当连续的图像帧在图像内容中基本不变化时，相位量表示采样时钟的最佳相位变化。 如果图像内容显着变化，则可以禁用相位调整。

公开(公告)号：US6028571A

公开(公告)日：2000-02-22

申请号：US35261

申请日：1998-03-05

申请人： Alexander Julian Eglit

发明人： Alexander Julian Eglit

IPC分类号： G09G3/20 ,  G09G5/00

CPC分类号： G09G5/006

摘要： A digital display unit which accurately determines a graphics source mode using which an analog display signal has been generated. Accurate determination of the source mode enables images encoded in the received display signal to be reproduced properly on a digital display screen. Some of the display signal parameters are measured by examining the display signal. The measured parameters are compared with corresponding stored parameters for each stored mode. A match of parameters is deemed to exist if the compared values are within an associated tolerance level. A source mode matching with all matching parameter is selected to process a display signal. The tolerance level is adaptively varied to select a suitable source mode.

摘要翻译： 一种数字显示单元，其准确地确定已经生成模拟显示信号的图形源模式。 准确地确定源模式使得在数字显示屏上正确地再现所接收的显示信号中编码的图像。 通过检查显示信号来测量一些显示信号参数。 将测量的参数与每个存储模式的相应存储参数进行比较。 如果比较值在相关的公差水平内，则认为参数匹配存在。 选择与所有匹配参数匹配的源模式来处理显示信号。 自适应地改变公差水平以选择合适的源模式。

公开(公告)号：US5703618A

公开(公告)日：1997-12-30

申请号：US561907

申请日：1995-11-22

申请人： Alexander Julian Eglit

发明人： Alexander Julian Eglit

IPC分类号： G09G5/00 ,  G06T3/40 ,  G09G5/36 ,  G06K9/36

CPC分类号： G06T3/4007

摘要： A graphics controller circuit for upscaling source video image to generate an upscaled video image. The graphics controller circuit generates additional pixel data for the upscaled video image by interpolating source video pixel data of a one scan line and an another scan line. However, when source video pixel data of the another scan line may not be available for interpolation, the graphics controller circuit generates additional pixel data from source video pixel data of only the one scan line. Source video pixel data of the another scan line may not be available, for example, as a bus that transfers the pixel data may not have sufficient amount of bandwidth.

摘要翻译： 一种用于升级源视频图像以生成放大的视频图像的图形控制器电路。 图形控制器电路通过内插一条扫描线和另一条扫描线的源视频像素数据来产生用于放大的视频图像的附加像素数据。 然而，当另一扫描线的源视频像素数据可能不可用于插值时，图形控制器电路从仅一条扫描线的源视频像素数据生成附加像素数据。 另一条扫描线的源视频像素数据可能不可用，例如，传输像素数据的总线可能没有足够的带宽量。