公开(公告)号：US08031731B2

公开(公告)日：2011-10-04

申请号：US12135368

申请日：2008-06-09

申请人： James J. Yu ,  Andrew C. Yang

发明人： James J. Yu ,  Andrew C. Yang

IPC分类号： H04L12/66

CPC分类号： H04L49/30 ,  H04L49/201 ,  H04L49/351 ,  H04L49/354

摘要： A system for sharing a network port of a network interface includes a plurality of processing units, a first network interface unit coupled to a first portion of the plurality of processing units, a second network interface unit coupled to a different portion of the plurality of processing units, and a link coupled between the first and second network interface units. The first and second network interface units each includes an independently controllable network port for connection to a network, and a virtual interface. The network port includes a shared MAC unit, a link interface, and control logic, which may selectably route packets between processing units of the first portion of the plurality of processing units and the network via the link and the network port of the second network interface unit. The virtual interface may include a plurality of independent programmable virtual MAC units.

摘要翻译： 用于共享网络接口的网络端口的系统包括多个处理单元，耦合到多个处理单元的第一部分的第一网络接口单元，耦合到多个处理的不同部分的第二网络接口单元 单元，以及耦合在第一和第二网络接口单元之间的链路。 第一和第二网络接口单元各自包括用于连接到网络的可独立控制的网络端口和虚拟接口。 网络端口包括共享MAC单元，链路接口和控制逻辑，其可以经由链路和第二网络接口的网络端口在多个处理单元的第一部分的处理单元和网络之间可选地路由分组 单元。 虚拟接口可以包括多个独立的可编程虚拟MAC单元。

公开(公告)号：US4714314A

公开(公告)日：1987-12-22

申请号：US698721

申请日：1985-02-06

申请人： Andrew C. Yang ,  Richard Payne ,  Richard A. Soref

发明人： Andrew C. Yang ,  Richard Payne ,  Richard A. Soref

IPC分类号： G02B6/14 ,  H04B10/2581 ,  G02B6/36

CPC分类号： H04B10/2581 ,  G02B6/14 ,  Y10S372/70

摘要： A mode dependent, optical time delay system for electrical signals having a highly multi-mode optical fiber having a step index profile in optical alignment with an optical source which is capable of converting an incoming electrical signal into an optical signal. By incorporating within the system a number of different components to alter or control the mode angles of the incoming optical signal, the resultant optical output signal is time delayed as it propagates through the optical fiber. This optical output signal is thereafter converted into an electrical output signal which is also time delayed in direct relation to the mode angle of the optical signal propagating through the optical fiber.

摘要翻译： 一种模式相关的光学时间延迟系统，用于具有高度多模光纤的电信号，其具有与能够将输入的电信号转换为光信号的光源对准的阶跃折射率分布。 通过在系统内并入多个不同的组件来改变或控制输入光信号的模式角，所产生的光输出信号在其通过光纤传播时被延时。 该光输出信号此后转换为与通过光纤传播的光信号的模式角直接相关的时间延迟的电输出信号。

公开(公告)号：US20090304002A1

公开(公告)日：2009-12-10

申请号：US12135368

申请日：2008-06-09

申请人： James J. Yu ,  Andrew C. Yang

发明人： James J. Yu ,  Andrew C. Yang

IPC分类号： H04L12/56

CPC分类号： H04L49/30 ,  H04L49/201 ,  H04L49/351 ,  H04L49/354

摘要： A system for sharing a network port of a network interface includes a plurality of processing units, a first network interface unit coupled to a first portion of the plurality of processing units, a second network interface unit coupled to a different portion of the plurality of processing units, and a link coupled between the first and second network interface units. The first and second network interface units each includes an independently controllable network port for connection to a network, and a virtual interface. The network port includes a shared MAC unit, a link interface, and control logic, which may selectably route packets between processing units of the first portion of the plurality of processing units and the network via the link and the network port of the second network interface unit. The virtual interface may include a plurality of independent programmable virtual MAC units.

摘要翻译： 用于共享网络接口的网络端口的系统包括多个处理单元，耦合到多个处理单元的第一部分的第一网络接口单元，耦合到多个处理的不同部分的第二网络接口单元 单元，以及耦合在第一和第二网络接口单元之间的链路。 第一和第二网络接口单元各自包括用于连接到网络的可独立控制的网络端口和虚拟接口。 网络端口包括共享MAC单元，链路接口和控制逻辑，其可以经由链路和第二网络接口的网络端口在多个处理单元的第一部分的处理单元和网络之间可选地路由分组 单元。 虚拟接口可以包括多个独立的可编程虚拟MAC单元。

公开(公告)号：US4005327A

公开(公告)日：1977-01-25

申请号：US625799

申请日：1975-10-28

申请人： Sven A. Roosild ,  Freeman D. Shepherd, Jr. ,  Andrew C. Yang

发明人： Sven A. Roosild ,  Freeman D. Shepherd, Jr. ,  Andrew C. Yang

IPC分类号： H01J29/45 ,  H01J31/49

CPC分类号： H01J29/455

摘要： A solid state sensing retina for infrared vidicon television camera tubes using a low voltage electron beam, consisting of a monolithic silicon wafer having an n-type substrate and two dimensional array of p-type islands, each island has a Schottky electrode photoemitter and substrate contact buss, an ohmic contact pad allows charging of the p-type region beneath the Schottky electrode.

摘要翻译： 一种用于使用低电压电子束的红外摄像机电视摄像机管的固态感测视网膜，由具有n型衬底和二维阵列的p型岛的单片硅晶片组成，每个岛具有肖特基电极光电发射器和衬底接触 总线，欧姆接触焊盘允许对肖特基电极下方的p型区域充电。

公开(公告)号：US07333468B1

公开(公告)日：2008-02-19

申请号：US11129798

申请日：2005-05-16

申请人： Sebastian Turullols ,  Aly E. Orady ,  James J. Yu ,  Andrew C. Yang

发明人： Sebastian Turullols ,  Aly E. Orady ,  James J. Yu ,  Andrew C. Yang

IPC分类号： H04J3/24 ,  H04J3/06 ,  H04L12/56 ,  H04L7/00 ,  H04L7/04 ,  H04L9/00 ,  H04B1/18 ,  H04B1/10

CPC分类号： H04J3/0632 ,  H03L7/093 ,  H03L2207/50 ,  H04N21/4305 ,  H04N21/4344

摘要： A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.

摘要翻译： 分组流多路复用器可以包括用于跟踪与分组流相关联的源时钟频率的一个或多个控制回路（例如，数字锁相环）。 第一个控制环路可能会缓慢地将接收的时间戳和估计时间戳之间的错误驱动为零。 第二个控制循环可以更快地将误差的一阶导数驱动到零。 第二控制循环可以包括根据跟踪速度排序的一组数字滤波器。 最初选择最慢滤波器的输出用于更新源时钟频率估计。 随着时间的推移，连续选择更快的过滤器。 估计的源时钟频率用于在分组流发送到输出信道上时重新分组分组流的分组。

公开(公告)号：US07912082B2

公开(公告)日：2011-03-22

申请号：US12135348

申请日：2008-06-09

申请人： Andrew C. Yang ,  James J. Yu

发明人： Andrew C. Yang ,  James J. Yu

IPC分类号： H04L12/66

CPC分类号： H04L49/9063 ,  H04L49/90

摘要： A system includes one or more processing units coupled to a network interface unit. The network interface unit may include a network port for connection to a network and a virtual interface that may be configured to distribute an available communication bandwidth of the network port between the one or more processing units. The network port may include a shared media access control (MAC) unit. The virtual interface may include a plurality of processing unit resources each associated with a respective one of the one or more processing units. Each of the processing unit resources may include an I/O interface unit coupled to a respective one of the one or more processing units via an I/O interconnect, and an independent programmable virtual MAC unit that is programmably configured by the respective one of the one or more processing units. The virtual interface may also include a receive datapath and a transmit datapath that are coupled between and shared by the plurality of processing unit resources and the network port.

摘要翻译： 系统包括耦合到网络接口单元的一个或多个处理单元。 网络接口单元可以包括用于连接到网络的网络端口和可被配置为在一个或多个处理单元之间分配网络端口的可用通信带宽的虚拟接口。 网络端口可以包括共享介质访问控制（MAC）单元。 虚拟接口可以包括多个处理单元资源，每个处理单元与一个或多个处理单元中的相应一个相关联。 每个处理单元资源可以包括通过I / O互连耦合到一个或多个处理单元中的相应一个处理单元的I / O接口单元，以及独立可编程虚拟MAC单元，其可编程地由 一个或多个处理单元。 虚拟接口还可以包括在多个处理单元资源和网络端口之间耦合并共享的接收数据路径和发送数据路径。

公开(公告)号：US07738498B1

公开(公告)日：2010-06-15

申请号：US11199627

申请日：2005-08-09

申请人： James J. Yu ,  Andrew C. Yang

发明人： James J. Yu ,  Andrew C. Yang

IPC分类号： H04J3/06

CPC分类号： H04J3/0685 ,  H03L7/06 ,  H04J3/047 ,  H04J3/0632 ,  H04N21/4305

摘要： A system including a memory (storing a set of data records), a digital phase-locked loop (PLL) and digital circuitry. Each of the data records is allocated to one packet stream in a set of packet streams. The digital circuitry is configured to: invoke a read operation from the memory in response to a received stream indicator and received channel indicator corresponding to a current timestamp-bearing packet; generate an output timestamp for the current packet equal to an expected timestamp provided by the memory as part of the read operation; and generate error data based on argument data including a received input timestamp, a received slot delay value, a previous source frequency estimate and an expected timestamp provided as part of the read operation. The digital PLL is configured to compute an updated source frequency estimate based on information including the error data and the previous source frequency estimate.

摘要翻译： 包括存储器（存储一组数据记录），数字锁相环（PLL）和数字电路的系统。 每个数据记录被分配给一组分组流中的一个分组流。 数字电路被配置为：响应于接收的流指示符和对应于当前时间戳的分组的接收的信道指示符，从存储器调用读取操作; 生成等于作为读操作的一部分由存储器提供的期望时间戳的当前分组的输出时间戳; 并且基于参数数据生成错误数据，包括接收到的输入时间戳，接收到的时隙延迟值，先前的源频率估计和作为读取操作的一部分提供的预期时间戳。 数字PLL被配置为基于包括误差数据和先前源频率估计的信息来计算更新的源频率估计。

公开(公告)号：US20090304022A1

公开(公告)日：2009-12-10

申请号：US12135348

申请日：2008-06-09

申请人： Andrew C Yang ,  James J. Yu

发明人： Andrew C Yang ,  James J. Yu

IPC分类号： H04L12/66

CPC分类号： H04L49/9063 ,  H04L49/90

摘要： A system includes one or more processing units coupled to a network interface unit. The network interface unit may include a network port for connection to a network and a virtual interface that may be configured to distribute an available communication bandwidth of the network port between the one or more processing units. The network port may include a shared media access control (MAC) unit. The virtual interface may include a plurality of processing unit resources each associated with a respective one of the one or more processing units. Each of the processing unit resources may include an I/O interface unit coupled to a respective one of the one or more processing units via an I/O interconnect, and an independent programmable virtual MAC unit that is programmably configured by the respective one of the one or more processing units. The virtual interface may also include a receive datapath and a transmit datapath that are coupled between and shared by the plurality of processing unit resources and the network port.

摘要翻译： 系统包括耦合到网络接口单元的一个或多个处理单元。 网络接口单元可以包括用于连接到网络的网络端口和可被配置为在一个或多个处理单元之间分配网络端口的可用通信带宽的虚拟接口。 网络端口可以包括共享介质访问控制（MAC）单元。 虚拟接口可以包括多个处理单元资源，每个处理单元与一个或多个处理单元中的相应一个相关联。 每个处理单元资源可以包括通过I / O互连耦合到一个或多个处理单元中的相应一个处理单元的I / O接口单元，以及独立可编程虚拟MAC单元，其可编程地由 一个或多个处理单元。 虚拟接口还可以包括在多个处理单元资源和网络端口之间耦合并共享的接收数据路径和发送数据路径。

公开(公告)号：US4857973A

公开(公告)日：1989-08-15

申请号：US049352

申请日：1987-05-14

申请人： Andrew C. Yang ,  Joseph P. Lorenzo ,  Richard A. Soref

发明人： Andrew C. Yang ,  Joseph P. Lorenzo ,  Richard A. Soref

IPC分类号： G02B6/42 ,  H01L31/108

CPC分类号： H01L31/108 ,  G02B6/42

摘要： The invention comprises a Schottky barrier type infrared photodetector which is monolithically integrated on a silicon waveguide. A Schottky barrier contact is positioned directly on a silicon waveguide to absorb grazing incidence optical signals passing through the waveguide. The Schottky contact is operated in the avalanche or reverse bias mode to generate a useable electrical signal.

摘要翻译： 本发明包括一个单片集成在硅波导上的肖特基势垒型红外光电探测器。 肖特基势垒接触件直接位于硅波导上以吸收通过波导的掠入射光信号。 肖特基触点以雪崩或反向偏置模式工作，以产生可用的电信号。