公开(公告)号：US10185566B2

公开(公告)日：2019-01-22

申请号：US13994142

申请日：2012-04-27

申请人： Alon Naveh ,  Yuval Yosef ,  Eliezer Weissmann ,  Anil Aggarwal ,  Efraim Rotem ,  Avi Mendelson ,  Ronny Ronen ,  Boris Ginzburg ,  Michael Mishaeli ,  Scott D. Hahn ,  David A. Koufaty ,  Ganapati Srinivasa ,  Guy Therien

发明人： Alon Naveh ,  Yuval Yosef ,  Eliezer Weissmann ,  Anil Aggarwal ,  Efraim Rotem ,  Avi Mendelson ,  Ronny Ronen ,  Boris Ginzburg ,  Michael Mishaeli ,  Scott D. Hahn ,  David A. Koufaty ,  Ganapati Srinivasa ,  Guy Therien

IPC分类号： G06F9/30 ,  G06F9/48 ,  G06F9/50

摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

公开(公告)号：US20140129808A1

公开(公告)日：2014-05-08

申请号：US13994142

申请日：2012-04-27

申请人： Alon Naveh ,  Yuval Yosef ,  Eliezer Weissmann ,  Anil Aggarwal ,  Efraim Rotem ,  Avi Mendelson ,  Ronny Ronen ,  Boris Ginzburg ,  Michael Mishaeli ,  Scott D. Hahn ,  David A. Koufaty ,  Ganapati Srinivasa ,  Guy Therien

发明人： Alon Naveh ,  Yuval Yosef ,  Eliezer Weissmann ,  Anil Aggarwal ,  Efraim Rotem ,  Avi Mendelson ,  Ronny Ronen ,  Boris Ginzburg ,  Michael Mishaeli ,  Scott D. Hahn ,  David A. Koufaty ,  Ganapati Srinivasa ,  Guy Therien

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/4856 ,  G06F9/5094 ,  G06F2209/5018 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/32

摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有第一和第二核心以独立执行指令的多核处理器，操作系统（OS）可见的第一核心和对OS可透明的第二核心，并且与第一核心不同。 可以包括在多核处理器中或耦合到多核处理器的任务控制器可以使由OS所安排的第一进程到OS的第一核心到第二核心的动态迁移到第二核心。 描述和要求保护其他实施例。

公开(公告)号：US09720730B2

公开(公告)日：2017-08-01

申请号：US13995994

申请日：2011-12-30

申请人： Boris Ginzburg ,  Ilya Osadchiy ,  Ronny Ronen ,  Eliezer Weissmann ,  Michael Mishaeli ,  Alon Naveh ,  David A. Koufaty ,  Scott D. Hahn ,  Tong Li ,  Avi Mendleson ,  Eugene Gorbatov ,  Hisham Abu-Salah ,  Dheeraj R. Subbareddy ,  Paolo Narvaez ,  Aamer Jaleel ,  Efraim Rotem ,  Yuval Yosef ,  Anil Aggarwal ,  Kenzo Van Craeynest

发明人： Boris Ginzburg ,  Ilya Osadchiy ,  Ronny Ronen ,  Eliezer Weissmann ,  Michael Mishaeli ,  Alon Naveh ,  David A. Koufaty ,  Scott D. Hahn ,  Tong Li ,  Avi Mendleson ,  Eugene Gorbatov ,  Hisham Abu-Salah ,  Dheeraj R. Subbareddy ,  Paolo Narvaez ,  Aamer Jaleel ,  Efraim Rotem ,  Yuval Yosef ,  Anil Aggarwal ,  Kenzo Van Craeynest

IPC分类号： G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F9/30 ,  G06F15/78

CPC分类号： G06F9/4881 ,  G06F9/30101 ,  G06F9/4856 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/24 ,  Y02D10/32

摘要： In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

公开(公告)号：US20140082630A1

公开(公告)日：2014-03-20

申请号：US13995994

申请日：2011-12-30

申请人： Boris Ginzburg ,  Ilya Osadchiy ,  Ronny Ronen ,  Eliezer Weissmann ,  Michael Mishaeli ,  Alon Naveh ,  David A. Koufaty ,  Scott D. Hahn ,  Tong Li ,  Avi Mendleson ,  Eugene Gorbatov ,  Hisham Abu-Salah ,  Dheeraj R. Subbareddy ,  Paolo Narvaez ,  Aamer Jaleel ,  Efraim Rotem ,  Yuval Yosef ,  Anil Aggarwal ,  Kenzo Van Craeynest

发明人： Boris Ginzburg ,  Ilya Osadchiy ,  Ronny Ronen ,  Eliezer Weissmann ,  Michael Mishaeli ,  Alon Naveh ,  David A. Koufaty ,  Scott D. Hahn ,  Tong Li ,  Avi Mendleson ,  Eugene Gorbatov ,  Hisham Abu-Salah ,  Dheeraj R. Subbareddy ,  Paolo Narvaez ,  Aamer Jaleel ,  Efraim Rotem ,  Yuval Yosef ,  Anil Aggarwal ,  Kenzo Van Craeynest

IPC分类号： G06F9/48

CPC分类号： G06F9/4881 ,  G06F9/30101 ,  G06F9/4856 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/24 ,  Y02D10/32

摘要： In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有第一和第二组核心的多核处理器。 第二组可以是与第一组或同一ISA组不同的指令集架构（ISA），但具有不同的功率和性能支持级别，并且对于操作系统（OS）是透明的。 处理器还包括迁移单元，其处理针对多个不同场景的迁移请求，并使上下文切换将进程从第二核心动态地迁移到第一组的第一核心。 这种基于动态硬件的上下文切换对于操作系统可以是透明的。 描述和要求保护其他实施例。

公开(公告)号：US10191742B2

公开(公告)日：2019-01-29

申请号：US13993668

申请日：2012-03-30

申请人： Efraim Rotem ,  Eliezer Weissmann ,  Boris Ginzburg ,  Alon Naveh ,  Nadav Shulman ,  Ronny Ronen

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Boris Ginzburg ,  Alon Naveh ,  Nadav Shulman ,  Ronny Ronen

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/34 ,  G06F9/38 ,  G06F11/30 ,  G06F11/34 ,  G06F1/32 ,  G06F9/455

摘要： A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data.

公开(公告)号：US20140019723A1

公开(公告)日：2014-01-16

申请号：US13993042

申请日：2011-12-28

申请人： Koichi Yamada ,  Ronny Ronen ,  Wei Li ,  Boris Ginzburg ,  Gadi Haber ,  Konstantin Levit-Gurevich ,  Esfir Natanzon ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

发明人： Koichi Yamada ,  Ronny Ronen ,  Wei Li ,  Boris Ginzburg ,  Gadi Haber ,  Konstantin Levit-Gurevich ,  Esfir Natanzon ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F1/3243 ,  G06F1/3293 ,  G06F9/30174 ,  G06F9/3808 ,  G06F9/4552 ,  G06F9/5094 ,  G06F15/7807 ,  Y02D10/122 ,  Y02D10/152 ,  Y02D10/22

摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code for execution on the ASMP is analyzed and a determination is made as to whether to allow the program code, or a code segment thereof to execute on a first core natively or to use binary translation on the code and execute the translated code on a second core which consumes less power than the first core during execution.

摘要翻译： 非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。 分析用于在ASMP上执行的程序代码，并且确定是否允许程序代码或其代码段在本地上在第一核上执行或者对代码使用二进制转换并且在 在执行过程中消耗的功率比第一个核心少的第二个核心。

公开(公告)号：US20130268742A1

公开(公告)日：2013-10-10

申请号：US13992710

申请日：2011-12-29

申请人： Koichi Yamada ,  Boris Ginzburg ,  Wei Li ,  Ronny Ronen ,  Esfir Natanzon ,  Konstantin Levit-Gurevich ,  Gadi Haber ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

发明人： Koichi Yamada ,  Boris Ginzburg ,  Wei Li ,  Ronny Ronen ,  Esfir Natanzon ,  Konstantin Levit-Gurevich ,  Gadi Haber ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/5044 ,  G06F9/5094 ,  Y02D10/22

摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.

摘要翻译： 非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。 在ASMP上执行的程序代码由二进制分析单元进行分析，以确定程序代码调用哪些函数，并选择哪些核执行程序代码或其代码段。 可以进行选择以提供程序代码的本地执行，以最小化功耗等等。 可以将基于该选择的控制操作插入到程序代码中，形成检测程序代码。 然后由ASMP执行检测的程序代码。

公开(公告)号：US09348594B2

公开(公告)日：2016-05-24

申请号：US13992710

申请日：2011-12-29

申请人： Koichi Yamada ,  Boris Ginzburg ,  Wei Li ,  Ronny Ronen ,  Esfir Natanzon ,  Konstantin Levit-Gurevich ,  Gadi Haber ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

发明人： Koichi Yamada ,  Boris Ginzburg ,  Wei Li ,  Ronny Ronen ,  Esfir Natanzon ,  Konstantin Levit-Gurevich ,  Gadi Haber ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

IPC分类号： G06F9/40 ,  G06F9/30 ,  G06F9/50

CPC分类号： G06F9/30181 ,  G06F9/5044 ,  G06F9/5094 ,  Y02D10/22

摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.

摘要翻译： 非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。 在ASMP上执行的程序代码由二进制分析单元进行分析，以确定程序代码调用哪些函数，并选择哪些核执行程序代码或其代码段。 可以进行选择以提供程序代码的本地执行，以最小化功耗等等。 可以将基于该选择的控制操作插入到程序代码中，形成检测程序代码。 然后由ASMP执行检测的程序代码。

公开(公告)号：US20140325184A1

公开(公告)日：2014-10-30

申请号：US13993668

申请日：2012-03-30

申请人： Efraim Rotem ,  Eliezer Weissamann ,  Boris Ginzburg ,  Alon Naveh ,  Nadav Shulman ,  Ronny Ronen

发明人： Efraim Rotem ,  Eliezer Weissamann ,  Boris Ginzburg ,  Alon Naveh ,  Nadav Shulman ,  Ronny Ronen

IPC分类号： G06F9/30

CPC分类号： G06F9/30083 ,  G06F1/3243 ,  G06F9/3836 ,  G06F9/4552 ,  G06F11/3062 ,  G06F11/3409 ,  G06F2201/865 ,  Y02D10/152 ,  Y02D10/34

摘要： A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data.

摘要翻译： 处理器可以节省微架构上下文以提高代码执行和电源管理的效率。 运行期间的电源管理硬件监视代码块的执行。 代码块已被编译成在代码块的一端附加保留空间。 保留空间包括与代码块相关联的元数据块或元数据块的标识符。 硬件将处理器的微架构上下文存储在元数据块中。 微架构上下文包括由代码块的第一次执行产生的性能数据。 硬件在代码块的第二次执行时读取元数据块，并根据性能数据调整第二次执行。

公开(公告)号：US09396020B2

公开(公告)日：2016-07-19

申请号：US13993273

申请日：2012-03-30

申请人： Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann ,  Karthikeyan Vaithianathan ,  Ehud Cohen

发明人： Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann ,  Karthikeyan Vaithianathan ,  Ehud Cohen

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/461 ,  G06F9/485

摘要： An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general purpose CPU has functional unit logic circuitry to execute an instruction that returns an amount of storage space to store context information of the accelerator.

摘要翻译： 描述了具有多个芯的装置，每个芯具有：a）加速器; 和b）耦合到加速器的通用CPU。 通用CPU具有功能单元逻辑电路，以执行返回一定量的存储空间以存储加速器的上下文信息的指令。