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公开(公告)号：US08984199B2
公开(公告)日：2015-03-17
申请号：US10631522
申请日：2003-07-31
CPC分类号： G06F9/4812 , G06F9/544
摘要： According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.
摘要翻译： 根据本发明的实施例，描述了用于多处理器系统中的处理器间中断的方法和装置。 一个实施例包括将处理器间中断请求写入第一存储器位置; 监控第一个内存位置; 检测第一存储器位置中的处理器间中断请求; 调用处理器间中断请求的功能; 并执行处理器间中断请求的功能。
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公开(公告)号：US07328293B2
公开(公告)日：2008-02-05
申请号：US11716377
申请日：2007-03-09
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.
摘要翻译： 提供了一种使用监视器 - 内存等待监视锁定的方法，装置和系统。 根据一个实施例，监视与竞争锁相关联的节点; 并且寻求有争议的锁的处理器进入休眠状态直到发生监视事件。
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公开(公告)号：US07640384B2
公开(公告)日：2009-12-29
申请号：US11903249
申请日：2007-09-20
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. In one embodiment, a memory to store instructions to perform functions of a monitoring mechanism is provided. The monitoring mechanism having a first logic to cause a processor to exit a sleep state in response to an event, wherein exiting the sleep state comprises resuming control of processing resources that were relinquished by the processor during the sleep state. The monitoring mechanism having a second logic to disable monitoring of a node associated with a contended lock after the processor exits the sleep state.
摘要翻译： 提供了一种使用监视器 - 内存等待监视锁定的方法，装置和系统。 在一个实施例中，提供了存储用于执行监视机制的功能的指令的存储器。 监视机制具有使处理器响应于事件退出休眠状态的第一逻辑，其中退出休眠状态包括恢复处理在休眠状态期间被处理器放弃的处理资源的控制。 所述监视机制具有第二逻辑，以在所述处理器退出所述睡眠状态之后禁用与竞争锁相关联的节点的监视。
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公开(公告)号：US07213093B2
公开(公告)日：2007-05-01
申请号：US10608708
申请日：2003-06-27
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.
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5.发明授权Programmable event driven yield mechanism which may activate service threads 有权可编程事件驱动的产生机制，可以激活服务线程公开(公告)号：US07849465B2
公开(公告)日：2010-12-07
申请号：US11134687
申请日：2005-05-19
申请人： Xiang Zou , Hong Wang , Scott Dion Rodgers , Darrell D. Boggs , Bryant Bigbee , Shivanandan Kaushik , Anil Aggarwal , Ittai Anati , Doron Orenstein , Per Hammarlund , John Shen , Larry O. Smith , James B. Crossland , Chris J. Newburn
发明人： Xiang Zou , Hong Wang , Scott Dion Rodgers , Darrell D. Boggs , Bryant Bigbee , Shivanandan Kaushik , Anil Aggarwal , Ittai Anati , Doron Orenstein , Per Hammarlund , John Shen , Larry O. Smith , James B. Crossland , Chris J. Newburn
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009 , G06F9/4843 , G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.
摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。 收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。 响应于条件，可以在操作系统的有限干预下激活服务线程。 在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。 该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。 可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。 还描述和要求保护其他实施例。
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6.发明授权公开(公告)号：US07627706B2
公开(公告)日：2009-12-01
申请号：US11850782
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括用于接收物理处理器标识号的逻辑中断识别号码创建逻辑，并通过使用物理处理器标识号创建逻辑处理器标识号。 每个逻辑处理器识别号对应于物理处理器识别号之一，并且逻辑处理器标识号各自包括处理器群标识号和群内标识号。 每个处理器集群标识号被形成为包括从相应的物理处理器标识号码位置移位的一组位，并且群内标识号分别响应于对应的物理处理器标识的其他位的值而形成 数。 描述其他实施例。
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公开(公告)号：US20090070511A1
公开(公告)日：2009-03-12
申请号：US11850790
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
IPC分类号： G06F13/24
CPC分类号： G06F9/505 , G06F9/3885 , G06F9/3891 , G06F9/5094 , G06F13/24 , Y02D10/14 , Y02D10/22
摘要： In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
摘要翻译： 在一些实施例中，一种装置包括处理器选择逻辑，以接收与每个具有处理器集群标识号的中断相关联的逻辑目的地标识号，以识别中断指向的处理器的集群。 逻辑目的地识别号码各自用于识别所识别的处理器簇内的哪些处理器可用于接收相应的一个中断。 处理器选择逻辑是选择一个可用的处理器来接收中断，并且通过逻辑目的地标识号中的对应位的相对位置来识别所选择的一个可用处理器。 描述其他实施例。
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公开(公告)号：US07769938B2
公开(公告)日：2010-08-03
申请号：US11850790
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
CPC分类号： G06F9/505 , G06F9/3885 , G06F9/3891 , G06F9/5094 , G06F13/24 , Y02D10/14 , Y02D10/22
摘要： In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
摘要翻译： 在一些实施例中，一种装置包括处理器选择逻辑，以接收与每个具有处理器集群标识号的中断相关联的逻辑目的地标识号，以识别中断指向的处理器的集群。 逻辑目的地识别号码各自用于识别所识别的处理器簇内的哪些处理器可用于接收相应的一个中断。 处理器选择逻辑是选择一个可用的处理器来接收中断，并且通过逻辑目的地标识号中的对应位的相对位置来识别所选择的一个可用处理器。 描述其他实施例。
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公开(公告)号：US07673090B2
公开(公告)日：2010-03-02
申请号：US10028858
申请日：2001-12-19
申请人： Shivnandan D. Kaushik , Ling Cen , James B. Crossland , Mohan J. Kumar , Linda J. Rankin , David J. O'Shea
发明人： Shivnandan D. Kaushik , Ling Cen , James B. Crossland , Mohan J. Kumar , Linda J. Rankin , David J. O'Shea
CPC分类号： G06F13/4081
摘要： Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.
摘要翻译： 包括处理器，存储器和/或I / O集线器的热插拔模块可以被添加到正在运行的计算设备和从运行的计算设备移除，而不需要重新启动正在运行的计算设备。 热插拔模块和计算设备包括热插拔接口，其支持热插拔模块和热插拔模块的热插拔。
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10.发明授权公开(公告)号：US07376775B2
公开(公告)日：2008-05-20
申请号：US10749929
申请日：2003-12-29
申请人： Lily Pao Looi , Stanley Steven Kulick , Dean A Mulla , Ashish Gupta , Keith R. Pflederer , Shivnandan D. Kaushik , Mohan J. Kumar , James B. Crossland
发明人： Lily Pao Looi , Stanley Steven Kulick , Dean A Mulla , Ashish Gupta , Keith R. Pflederer , Shivnandan D. Kaushik , Mohan J. Kumar , James B. Crossland
IPC分类号： G06F13/00
CPC分类号： G06F11/1666 , G06F13/16
摘要： In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.
摘要翻译： 在一些实施例中，一种装置包括处理器，扩展器存储器桥位置，耦合到扩展器存储器桥位置的存储器，以及总线控制器，其包括拦截和阻止从处理器到扩展器存储器桥位置的通信的截距逻辑，并且模拟 一个扩展记忆桥。 在一些实施例中，一种方法包括拦截和阻止对设备的状态请求，而不管该设备是否被安装，以及响应状态请求。
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