公开(公告)号：US07100002B2

公开(公告)日：2006-08-29

申请号：US10663327

申请日：2003-09-16

申请人： Steven Shrader ,  Samitinjoy Pal ,  Anne Espinoza ,  Michael McKeon

发明人： Steven Shrader ,  Samitinjoy Pal ,  Anne Espinoza ,  Michael McKeon

IPC分类号： G06F12/00

CPC分类号： G06F13/1673

摘要： A port independent data transaction interface for multi-port devices is provided. The port independent data transaction interface includes a command channel that receives command data and a source id. The source id indicates a source device that transmitted the command data. In addition, a data-in channel is included that receives write data and a write source id. Similar to the source id, the write source id indicates a source device that transmitted the write data. The port independent data transaction interface further includes a data-out channel that provides read data and a read id. The read id indicates a source device that transmitted a read command corresponding to the read data. The port independent data transaction interface utilizes the source id to associate command data with corresponding write data and read data.

摘要翻译： 提供了一种用于多端口设备的端口独立数据事务接口。 端口独立数据事务接口包括接收命令数据和源ID的命令通道。 源id表示发送命令数据的源设备。 此外，包括接收写入数据和写入源id的数据输入通道。 与源id类似，写入源id表示发送写入数据的源设备。 端口独立数据事务接口还包括提供读取数据和读取ID的数据输出通道。 读取ID指示发送与读取数据相对应的读取命令的源设备。 端口独立数据事务接口利用源ID将命令数据与相应的写入数据和读取数据相关联。

公开(公告)号：US08098535B2

公开(公告)日：2012-01-17

申请号：US12413998

申请日：2009-03-30

申请人： John MacLaren ,  Anne Espinoza

发明人： John MacLaren ,  Anne Espinoza

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C8/18 ,  G11C2207/2254

摘要： An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the a data strobe signal is repeatedly sampled at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal. The fine delay is a period of time shorter than the coarse delay. Once the rising edge is found, the coarse delay is removed from the gate assert time, thus setting the gate assert time centrally within the preamble of the data strobe signal.

摘要翻译： 提供了一种用于存储器接口中的门训练的发明。 本发明包括将粗延迟添加到门断言时间，其中粗延迟是预定义的时间段，并且门断言时间是数据选通门信号被断言的时间。 接下来，数据选通信号在门断言时刻被重复采样，直到找到数据选通信号的上升沿，其中在数据选通信号的采样之间的门断言时间附加了微小的延迟。 精细延迟是比粗延迟短的时间段。 一旦找到上升沿，粗略的延迟就从门断开时间去除，从而在数据选通信号的前导码内集中设置门断言时间。

公开(公告)号：US07952945B2

公开(公告)日：2011-05-31

申请号：US12414044

申请日：2009-03-30

申请人： Anne Espinoza ,  John MacLaren

发明人： Anne Espinoza ,  John MacLaren

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C2207/2254

摘要： An invention is provided for determining write leveling delay for a plurality of memory devices having command signals lines connected in series to each memory device is disclosed. The invention includes determining a device delay value for each memory device. Each device delay value indicates a period of time to delay a DQS signal when accessing a related memory device. Once these delay values are determined, the delay values are examined sequentially and a prior device delay value is set to a lower value, for example zero, when a subsequent device delay value of a memory device connected subsequently along the command signal lines is greater than the prior device delay value.

摘要翻译： 提供了一种用于确定具有与每个存储器件串联连接的命令信号线的多个存储器件的写入调平延迟的发明。 本发明包括确定每个存储器件的器件延迟值。 每个设备延迟值指示在访问相关存储器件时延迟DQS信号的时间段。 一旦确定了这些延迟值，则当随后沿着命令信号线连接的存储器件的后续器件延迟值大于等于当前器件延迟值被设置为较低值（例如为零）时，延迟值被顺序地检查 先前的设备延迟值。

公开(公告)号：US20100287401A1

公开(公告)日：2010-11-11

申请号：US12435550

申请日：2009-05-05

申请人： Anne Espinoza ,  John MacLaren

发明人： Anne Espinoza ,  John MacLaren

IPC分类号： G06F13/42 ,  G11C8/18 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G06F13/1689 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

摘要： An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal. The invention includes determining a phase shift relationship between the source clock signal and a signal. When the phase shift relationship is below a predetermined threshold the data is transferred between the source clock domain and the receiving clock domain using a first plurality of stage operations. When the phase shift relationship is above the predetermined threshold, the data is transferred between the source clock domain and the receiving clock domain using a second plurality of stage operations that delay data transfer an additional half period of the source clock signal.

摘要翻译： 提供了一种用于在异步时钟域之间传送数据的发明。 异步时钟域包括用源时钟信号操作的源时钟域和以接收时钟信号操作的接收时钟域。 本发明包括确定源时钟信号和信号之间的相移关系。 当相移关系低于预定阈值时，使用第一多个阶段操作在源时钟域和接收时钟域之间传送数据。 当相移关系高于预定阈值时，使用延迟数据传送源时钟信号的附加半周期的第二多个级操作，在源时钟域和接收时钟域之间传送数据。

公开(公告)号：US08429438B2

公开(公告)日：2013-04-23

申请号：US12435550

申请日：2009-05-05

申请人： Anne Espinoza ,  John MacLaren

发明人： Anne Espinoza ,  John MacLaren

IPC分类号： G06F1/12

CPC分类号： G11C7/1051 ,  G06F13/1689 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

摘要： An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal. The invention includes determining a phase shift relationship between the source clock signal and a signal. When the phase shift relationship is below a predetermined threshold the data is transferred between the source clock domain and the receiving clock domain using a first plurality of stage operations. When the phase shift relationship is above the predetermined threshold, the data is transferred between the source clock domain and the receiving clock domain using a second plurality of stage operations that delay data transfer an additional half period of the source clock signal.

摘要翻译： 提供了一种用于在异步时钟域之间传送数据的发明。 异步时钟域包括用源时钟信号操作的源时钟域和以接收时钟信号操作的接收时钟域。 本发明包括确定源时钟信号和信号之间的相移关系。 当相移关系低于预定阈值时，使用第一多个阶段操作在源时钟域和接收时钟域之间传送数据。 当相移关系高于预定阈值时，使用延迟数据传送源时钟信号的附加半周期的第二多个级操作，在源时钟域和接收时钟域之间传送数据。

公开(公告)号：US20100246291A1

公开(公告)日：2010-09-30

申请号：US12414044

申请日：2009-03-30

申请人： Anne Espinoza ,  John MacLaren

发明人： Anne Espinoza ,  John MacLaren

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C2207/2254

摘要： An invention is provided for determining write leveling delay for a plurality of memory devices having command signals lines connected in series to each memory device is disclosed. The invention includes determining a device delay value for each memory device. Each device delay value indicates a period of time to delay a DQS signal when accessing a related memory device. Once these delay values are determined, the delay values are examined sequentially and a prior device delay value is set to a lower value, for example zero, when a subsequent device delay value of a memory device connected subsequently along the command signal lines is greater than the prior device delay value.

摘要翻译： 提供了一种用于确定具有与每个存储器件串联连接的命令信号线的多个存储器件的写入调平延迟的发明。 本发明包括确定每个存储器件的器件延迟值。 每个设备延迟值指示在访问相关存储器件时延迟DQS信号的时间段。 一旦确定了这些延迟值，则当随后沿着命令信号线连接的存储器件的后续器件延迟值大于等于当前器件延迟值被设置为较低值（例如为零）时，延迟值被顺序地检查 先前的设备延迟值。

公开(公告)号：US20100246290A1

公开(公告)日：2010-09-30

申请号：US12413998

申请日：2009-03-30

申请人： John MacLaren ,  Anne Espinoza

发明人： John MacLaren ,  Anne Espinoza

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C8/18 ,  G11C2207/2254

摘要： An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the a data strobe signal is repeatedly sampled at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal. The fine delay is a period of time shorter than the coarse delay. Once the rising edge is found, the coarse delay is removed from the gate assert time, thus setting the gate assert time centrally within the preamble of the data strobe signal.

摘要翻译： 提供了一种用于存储器接口中的门训练的发明。 本发明包括将粗延迟添加到门断言时间，其中粗延迟是预定义的时间段，并且门断言时间是数据选通门信号被断言的时间。 接下来，数据选通信号在门断言时刻被重复采样，直到找到数据选通信号的上升沿，其中在数据选通信号的采样之间的门断言时间附加了微小的延迟。 精细延迟是比粗延迟短的时间段。 一旦找到上升沿，粗略的延迟就从门断开时间去除，从而在数据选通信号的前导码内集中设置门断言时间。

公开(公告)号：US20050060501A1

公开(公告)日：2005-03-17

申请号：US10663327

申请日：2003-09-16

申请人： Steven Shrader ,  Samitinjoy Pal ,  Anne Espinoza ,  Michael McKeon

发明人： Steven Shrader ,  Samitinjoy Pal ,  Anne Espinoza ,  Michael McKeon

IPC分类号： G06F12/00 ,  G06F13/16

CPC分类号： G06F13/1673

摘要： A port independent data transaction interface for multi-port devices is provided. The port independent data transaction interface includes a command channel that receives command data and a source id. The source id indicates a source device that transmitted the command data. In addition, a data-in channel is included that receives write data and a write source id. Similar to the source id, the write source id indicates a source device that transmitted the write data. The port independent data transaction interface further includes a data-out channel that provides read data and a read id. The read id indicates a source device that transmitted a read command corresponding to the read data. The port independent data transaction interface utilizes the source id to associate command data with corresponding write data and read data.

摘要翻译： 提供了一种用于多端口设备的端口独立数据事务接口。 端口独立数据事务接口包括接收命令数据和源ID的命令通道。 源id表示发送命令数据的源设备。 此外，包括接收写入数据和写入源id的数据输入通道。 与源id类似，写入源id表示发送写入数据的源设备。 端口独立数据事务接口还包括提供读取数据和读取ID的数据输出通道。 读取ID指示发送与读取数据相对应的读取命令的源设备。 端口独立数据事务接口利用源ID将命令数据与相应的写入数据和读取数据相关联。