公开(公告)号：US07100002B2

公开(公告)日：2006-08-29

申请号：US10663327

申请日：2003-09-16

申请人： Steven Shrader ,  Samitinjoy Pal ,  Anne Espinoza ,  Michael McKeon

发明人： Steven Shrader ,  Samitinjoy Pal ,  Anne Espinoza ,  Michael McKeon

IPC分类号： G06F12/00

CPC分类号： G06F13/1673

摘要： A port independent data transaction interface for multi-port devices is provided. The port independent data transaction interface includes a command channel that receives command data and a source id. The source id indicates a source device that transmitted the command data. In addition, a data-in channel is included that receives write data and a write source id. Similar to the source id, the write source id indicates a source device that transmitted the write data. The port independent data transaction interface further includes a data-out channel that provides read data and a read id. The read id indicates a source device that transmitted a read command corresponding to the read data. The port independent data transaction interface utilizes the source id to associate command data with corresponding write data and read data.

摘要翻译： 提供了一种用于多端口设备的端口独立数据事务接口。 端口独立数据事务接口包括接收命令数据和源ID的命令通道。 源id表示发送命令数据的源设备。 此外，包括接收写入数据和写入源id的数据输入通道。 与源id类似，写入源id表示发送写入数据的源设备。 端口独立数据事务接口还包括提供读取数据和读取ID的数据输出通道。 读取ID指示发送与读取数据相对应的读取命令的源设备。 端口独立数据事务接口利用源ID将命令数据与相应的写入数据和读取数据相关联。

公开(公告)号：US07062625B1

公开(公告)日：2006-06-13

申请号：US10210858

申请日：2002-07-31

申请人： Steven Shrader ,  Art Gmurowski ,  Samitinjoy Pal ,  Michael McKeon

发明人： Steven Shrader ,  Art Gmurowski ,  Samitinjoy Pal ,  Michael McKeon

IPC分类号： G06F12/00

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

摘要： An interface for sending write data, write control signals and write data between a memory controller and a double data rate (DDR) memory with the appropriate timing relationships so that the write data can be reliably written in the DDR memory. Also, an interface for reliably capturing read data received from the DDR memory during a read operation.

摘要翻译： 用于以适当的时序关系在存储器控制器和双数据速率（DDR）存储器之间发送写入数据，写入控制信号和写入数据的接口，使写入数据可以可靠地写入DDR存储器。 而且，用于在读取操作期间可靠地捕获从DDR存储器接收的读取数据的接口。

公开(公告)号：US06665230B1

公开(公告)日：2003-12-16

申请号：US10211691

申请日：2002-07-31

申请人： Steven Shrader ,  Art Gmurowski ,  Samitinjoy Pal ,  Michael McKeon

发明人： Steven Shrader ,  Art Gmurowski ,  Samitinjoy Pal ,  Michael McKeon

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03K5/131 ,  H03K5/133 ,  H03K2005/00156

摘要： Circuitry for programming the amount of delay applied to an input signal, the circuitry performing the method of determining the number of delay elements required to capture a clock cycle, receiving a programmable delay value and calculating the number of delay elements required to delay a clock signal by the received delay value and delaying the clock signal by the number of delay elements required to delay the clock signal by the programmable delay value.

摘要翻译： 用于对施加到输入信号的延迟量进行编程的电路，所述电路执行确定捕获时钟周期所需的延迟元件的数量的方法，接收可编程延迟值并计算延迟时钟信号所需的延迟元件的数量 通过接收到的延迟值并将时钟信号延迟由时钟信号延迟可编程延迟值所需的延迟元件的数量。

公开(公告)号：US08402249B1

公开(公告)日：2013-03-19

申请号：US12903055

申请日：2010-10-12

申请人： Jun Zhu ,  Joseph Jun Cao ,  Samitinjoy Pal ,  Hongyan Liu ,  Can Ma

发明人： Jun Zhu ,  Joseph Jun Cao ,  Samitinjoy Pal ,  Hongyan Liu ,  Can Ma

IPC分类号： G06F12/10

CPC分类号： G06F12/0207 ,  G06F12/0292 ,  Y02D10/13

摘要： A method of mapping system addresses to physical addresses associated with a physical memory device receives memory requirements associated with an application, allocates a region of the physical memory device to the application (wherein the region is a contiguous portion of the physical addresses that does not overlap with any other region and is associated with a memory mapping mode), determines a memory mapping scheme for the region (wherein the memory mapping scheme defines the mapping between system addresses and the region and is based at least on the memory mapping mode) and modifies a mapping register to reflect the region. In one implementation, the method modifies the mapping register to reflect the memory mapping scheme. In another implementation, the memory requirements comprise an application type, and the memory mapping mode is determined based on the application type.

摘要翻译： 将系统地址映射到与物理存储器设备相关联的物理地址的方法接收与应用相关联的存储器需求，将物理存储器设备的区域分配给应用（其中该区域是不重叠的物理地址的连续部分 与任何其他区域相关联并与存储器映射模式相关联），确定该区域的存储器映射方案（其中存储器映射方案定义系统地址与该区域之间的映射，并且至少基于存储器映射模式）并且修改 一个映射寄存器来反映该区域。 在一个实现中，该方法修改映射寄存器以反映存储器映射方案。 在另一实现中，存储器需求包括应用类型，并且基于应用类型来确定存储器映射模式。

公开(公告)号：US20050060501A1

公开(公告)日：2005-03-17

申请号：US10663327

申请日：2003-09-16

申请人： Steven Shrader ,  Samitinjoy Pal ,  Anne Espinoza ,  Michael McKeon

发明人： Steven Shrader ,  Samitinjoy Pal ,  Anne Espinoza ,  Michael McKeon

IPC分类号： G06F12/00 ,  G06F13/16

CPC分类号： G06F13/1673

摘要： A port independent data transaction interface for multi-port devices is provided. The port independent data transaction interface includes a command channel that receives command data and a source id. The source id indicates a source device that transmitted the command data. In addition, a data-in channel is included that receives write data and a write source id. Similar to the source id, the write source id indicates a source device that transmitted the write data. The port independent data transaction interface further includes a data-out channel that provides read data and a read id. The read id indicates a source device that transmitted a read command corresponding to the read data. The port independent data transaction interface utilizes the source id to associate command data with corresponding write data and read data.

摘要翻译： 提供了一种用于多端口设备的端口独立数据事务接口。 端口独立数据事务接口包括接收命令数据和源ID的命令通道。 源id表示发送命令数据的源设备。 此外，包括接收写入数据和写入源id的数据输入通道。 与源id类似，写入源id表示发送写入数据的源设备。 端口独立数据事务接口还包括提供读取数据和读取ID的数据输出通道。 读取ID指示发送与读取数据相对应的读取命令的源设备。 端口独立数据事务接口利用源ID将命令数据与相应的写入数据和读取数据相关联。