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公开(公告)号：US20250103681A1
公开(公告)日：2025-03-27
申请号：US18890214
申请日：2024-09-19
Applicant: Arm Limited
Inventor： Olof Henrik Uhrenholt
Abstract: A processing element is configured to approximate a transcendental function. The processing element comprises an input storage and a look-up storage. The processing element obtains floating-point input data from the input storage representing having an input exponent value and an input mantissa value. The processing element looks up approximation parameters and an output exponent value from the look-up storage, wherein each group of approximation parameters and output exponent value are stored in the look-up storage in association with a respective range of a plurality of ranges that are defined by the input exponent value and the input mantissa value. The ranges cover values of the input exponent value and input mantissa value such that the output exponent value associated with each range does not change by more than a predetermined number. An approximation function is evaluated that approximates the transcendental function based on the looked-up approximation parameters and output exponent.
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公开(公告)号：US12260218B2
公开(公告)日：2025-03-25
申请号：US18343294
申请日：2023-06-28
Applicant: Arm Limited
Inventor： Quentin Éric Nouvel , Luca Nassi , Nicola Piano , Albin Pierrick Tonnerre , Geoffray Matthieu Lacourba
Abstract: There is provided an apparatus, method for data processing. The apparatus comprises post decode cracking circuitry responsive to receipt of decoded instructions from decode circuitry of a processing pipeline, to crack the decoded instructions into micro-operations to be processed by processing circuitry of the processing pipeline. The post decode cracking circuitry is responsive to receipt of a decoded instruction suitable for cracking into a plurality of micro-operations including at least one pair of micro-operations having a producer-consumer data dependency, to generate the plurality of micro-operations including a producer micro-operation and a consumer micro-operation, and to assign a transfer register to transfer data between the producer micro-operation and the consumer micro-operation.
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公开(公告)号：US20250087296A1
公开(公告)日：2025-03-13
申请号：US18243441
申请日：2023-09-07
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Khushal Gelda , Ramesh Manohar , Teresa Louise Mclaurin , Prashant Mohan Kulkarni
Abstract: Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.
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公开(公告)号：US12249400B2
公开(公告)日：2025-03-11
申请号：US17885747
申请日：2022-08-11
Applicant: Arm Limited
Inventor： Edward Martin McCombs, Jr.
Abstract: An on-chip memory is provided. The memory includes wordline sections, input/output (I/O) circuitry, and control circuitry. Each wordline section includes a number of wordlines, and each wordline section is coupled to a different wordline control circuitry. The control circuitry is configured to, in response to receiving an access request including an address, decode the address including determine, based on the address, an associated wordline, and determine, based on the associated wordline, an associated wordline section. The control circuitry is further configured to apply power to wordline control circuitry coupled to the associated wordline section, and access the address.
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公开(公告)号：US20250078224A1
公开(公告)日：2025-03-06
申请号：US18240674
申请日：2023-08-31
Applicant: Arm Limited
Inventor： David HANWELL
Abstract: Methods and systems for reducing the appearance of block-related artifacts are described. The methods include obtaining image frames in a sequence of image frames and adjusting some or all image frames in the sequence of image frames to generate adjusted image frames. The adjusted image frames may be created by generating image data and adding it to one or more edges of the image frame or by discarding image data from the image frame. The adjusted image frames shift a block origin relative to image data in the image frame. The adjusting is performed so that the shift of the block origin varies during the sequence of image frames. A block-based process is applied to each adjusted image frame to generate processed image frames, wherein blocks of image data are selected and processed in each adjusted frame of image data according to the block origin.
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Patent Agency Ranking
公开(公告)号：US20250077499A1
公开(公告)日：2025-03-06
申请号：US18240632
申请日：2023-08-31
Inventor： Marco SIRACUSA , Joshua RANDALL , Douglas James JOSEPH , Miquel MORETÓ PLANAS , Adrià ARMEJACH SANOSA
IPC: G06F16/22
Abstract: A data structure marshalling unit for a processor comprises data structure traversal circuitry to perform data structure traversal processing according to a dataflow architecture. The data structure traversal circuitry comprises two or more layers of traversal circuit units, each layer comprising two or more parallel lanes of traversal circuit units. Each traversal circuit unit triggers loading, according to a programmable iteration range, of at least one stream of elements of at least one data structure from data storage circuitry. For at least one programmable setting for the data structure traversal circuitry, the programmable iteration range for a given traversal circuit unit in a downstream layer is dependent on one or more elements of the at least one stream of elements loaded by at least one traversal circuit unit in an upstream layer. Output interface circuitry outputs to the data storage circuitry at least one vector of elements loaded by respective traversal circuit units in a given active layer of the data structure traversal circuitry.
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公开(公告)号：US20250077233A1
公开(公告)日：2025-03-06
申请号：US18459602
申请日：2023-09-01
Applicant: ARM Limited
Inventor： Houdhaifa BOUZGUARROU , Michael Brian SCHINZLER
Abstract: A data processing apparatus is provided. It includes history storage circuitry that stores historic data of instructions and prediction circuitry that predicts a historic datum of a specific instruction based on subsets of the historic data of the instructions. The history storage circuitry overwrites the historic data of one of the instructions to form a corrupted instruction datum and at least one of the subsets of the historic data of the instructions includes the corrupted historic datum.
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公开(公告)号：US12242856B2
公开(公告)日：2025-03-04
申请号：US17656346
申请日：2022-03-24
Applicant: Arm Limited
IPC: G06F9/38
Abstract: A data processor comprising an execution engine 51 for executing programs for execution threads and one or more caches 48, 49 operable to store data values for use when executing program instructions to perform processing operations for execution threads. The data processor further comprises a thread throttling control unit 54 configured to monitor the operation of the caches 48, 49 during execution of programs for execution threads, and to control the issuing of instructions for execution threads to the execution engine for executing a program based on the monitoring of the operation of the caches during execution of the program.
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公开(公告)号：US12242399B2
公开(公告)日：2025-03-04
申请号：US17678174
申请日：2022-02-23
Applicant: Arm Limited
Inventor： Jacob Joseph , Tessil Thomas , Arthur Brian Laughton , Anitha Kona , Jamshed Jalal
IPC: G06F13/00 , G06F12/0862 , G06F12/0891 , G06F12/1045 , G06F13/16
Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.
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公开(公告)号：US20250068427A1
公开(公告)日：2025-02-27
申请号：US18454158
申请日：2023-08-23
Applicant: Arm Limited
Abstract: An apparatus has pointer storage to store pointer values for a plurality of pointers and increment circuitry, responsive to a series of increment events, to differentially increment the pointer values of the pointers. Training circuitry comprises tracker circuitry to maintain a plurality of tracker entries and cache circuitry to maintain a plurality of cache entries. Each tracker entry identifies a control flow instruction, and each cache entry stores a resolved behaviour of an instance of a control flow instruction identified by a tracker entry. For a given control flow instruction identified in a given tracker entry, the training circuitry performs a training process to seek to determine, as an associated pointer for the given control flow instruction, a pointer from amongst the plurality of pointers whose pointer value increments in a manner that meets a correlation threshold with occurrence of instances of the given control flow instruction. Promotion circuitry, responsive to detection of the correlation threshold being met for the given control flow instruction, allocates a prediction entry within prediction circuitry to identify the given control flow instruction and the associated pointer, and a behaviour record is established within the prediction entry identifying the resolved behaviour for one or more instances of the given control flow instruction. The behaviour record is arranged such that each resolved behaviour is associated with the pointer value of the associated pointer at the time that resolved behaviour was observed. Responsive to a prediction trigger associated with a replay of a given instance of the given control flow instruction, the prediction circuitry determines, in dependence on a current pointer value of the associated pointer, a predicted behaviour of the given instance of the given control flow instruction from the behaviour record within the prediction entry.
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