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1.发明申请公开(公告)号：US20050122158A1
公开(公告)日：2005-06-09
申请号：US10732791
申请日：2003-12-09
IPC分类号： H03K17/16
CPC分类号： H03K17/164
摘要： A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.
摘要翻译： 具有经历高到低转换的接收信号的第一反相阈值的静态接收机，以及经历低到高转换的接收信号的第二反相阈值，其中第一反转阈值大于第二反转阈值。 一个实施例包括静态接收器，pFET和nFET，其中当在接收器的输入端口处接收到高电平到低电平的转换时，pFET耦合到输入端口，以有助于提高反转阈值， 并且当在输入端口处接收到低电平到高电平的转换时，nFET耦合到输入端口，以便有助于降低反转阈值。 描述和要求保护其他实施例。
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公开(公告)号：US06614680B2
公开(公告)日：2003-09-02
申请号：US10172277
申请日：2002-06-13
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.
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3.发明授权Integrated circuit bus architecture including a full-swing, clocked, common-gate receiver for fast on-chip signal transmission 有权集成电路总线架构，包括全频，时钟，共门接收器，用于快速片上信号传输公开(公告)号：US06353342B1
公开(公告)日：2002-03-05
申请号：US09702121
申请日：2000-10-30
IPC分类号： G11C706
CPC分类号： H04L25/0292 , H04L25/0278 , H04L25/028
摘要： An integrated circuit (IC) bus architecture is disclosed. The bus architecture includes a receiver for fast on-chip signal transmission. The receiver includes a first gate device having one terminal connected to a voltage source and a gate terminal connectable to receive a sense signal. A second gate device includes one terminal connected to another terminal of the first gate device, a gate terminal connectable to receive the sense signal and another terminal serving as an input terminal of the receiver and connectable to an interconnect bus to receive input signals from other components on the IC chip. The receiver also includes a third gate device having one terminal connected to a voltage source and another terminal serving as an output terminal of the receiver and connected to the other terminal of the first gate device. The receiver further includes an inverter having an input terminal connected to the output of the receiver and having an output terminal connected to a gate terminal of the third gate device. The input of the receiver is capable of being pre-discharged to a low signal and the output of the receiver is capable of being pre-charged to a high signal for substantially instantaneous transmission of input signals received by the receiver.
摘要翻译： 公开了一种集成电路（IC）总线架构。 总线架构包括用于快速片上信号传输的接收器。 接收机包括具有连接到电压源的一个端子和可连接以接收感测信号的栅极端子的第一栅极器件。 第二栅极器件包括连接到第一栅极器件的另一个端子的一个端子，可连接的感测信号的栅极端子和用作接收器的输入端子的另一个端子，并且可连接到互连总线以从其它部件接收输入信号 在IC芯片上。 接收机还包括具有连接到电压源的一个端子和用作接收器的输出端的另一个端子并连接到第一门装置的另一端的第三门装置。 接收机还包括一个反相器，其具有连接到接收器的输出的输入端，并且具有连接到第三门装置的栅极端的输出端。 接收机的输入能够被预放电到低信号，并且接收机的输出能够被预充电到高信号，以便接收器接收的输入信号的基本瞬时传输。
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4.发明授权公开(公告)号：US06351150B1
公开(公告)日：2002-02-26
申请号：US09658793
申请日：2000-09-11
IPC分类号： H03K19096
CPC分类号： H03K19/0016 , H03K19/01855
摘要： A high performance interconnect that utilizes dynamic driver technology is capable of reduced power operation during periods of low data switching activity. Circuitry is provided that limits the performance of an evaluation operation in the dynamic driver circuitry to clock cycles during which a present input bit of the interconnect differs from a previous input bit. Thus, the evaluation operation and subsequent precharge of the driver output is performed sparingly during periods of low data switching activity. An output circuit is also provided for decoding the data stream flowing through the interconnect at the receiver end thereof. Using the principles of the present invention, it is possible to achieve the performance advantages of dynamic drivers with the switching activity of interconnects that use static CMOS technology.
摘要翻译： 利用动态驱动技术的高性能互连能够在低数据交换活动期间降低功耗。 提供了电路，其将动态驱动器电路中的评估操作的性能限制为时钟周期，在该周期期间，互连的当前输入位与先前的输入位不同。 因此，在低数据切换活动的时段期间，谨慎地执行驱动器输出的评估操作和随后的预充电。 还提供了一个输出电路，用于解码在其接收端处流经互连的数据流。 使用本发明的原理，可以通过使用静态CMOS技术的互连的交换活动来实现动态驱动器的性能优点。
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公开(公告)号：US06751141B1
公开(公告)日：2004-06-15
申请号：US10305703
申请日：2002-11-26
IPC分类号： G11C702
摘要： A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.
摘要翻译： 一种用于读取SRAM中的存储单元的读出放大器，读出放大器包括两个栅极偏置的pMOSFET，每个对应于选定的位线。 两个栅极偏置的pMOSFET的栅极将其栅极偏置到偏置电压，其源极通过列选择晶体管耦合到所选位线，并且其漏极通过传输晶体管耦合到两个交叉耦合的反相器的两个端口， 交叉耦合的逆变器形成锁存器。 在选择的位线对已被预充电并且预充电阶段结束之后，两个栅极偏置的pMOSFET中的一个快速进入其亚阈值区域，其中一个位线通过其相应的存储单元放电，从而切断位线的电容 从感测放大器。 当通过晶体管使能时，两个pMOSFET中的另一个允许显着的位线电荷通过其对应的传输晶体管传输到其相应的端口，而相对较小的电荷被传送到另一个端口。 该电荷转移方案允许在端口处快速产生差分电压，从而以降低的功率消耗提供快速锁存和读取操作。 位线电压摆幅也可以降低以降低功耗。
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公开(公告)号：US06690205B2
公开(公告)日：2004-02-10
申请号：US10283933
申请日：2002-10-29
申请人： Atila Alvandpour
发明人： Atila Alvandpour
IPC分类号： H03K1901
CPC分类号： H03K19/0963
摘要： A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.
摘要翻译： 包含在集成电路内的多米诺逻辑电路包括动态逻辑电路和中间逻辑电路。 中间逻辑电路包括具有耦合到源电压线的源极端子和具有连接到低接地电压线的源极端子的n块晶体管的上拉晶体管。
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公开(公告)号：US06617890B1
公开(公告)日：2003-09-09
申请号：US10104393
申请日：2002-03-22
IPC分类号： H03K5153
CPC分类号： G01R19/16538 , G06F1/28 , H03K5/08 , H03K5/153
摘要： A system for measuring the stability of a power signal from a power supply includes a threshold violation detector. The threshold violation detector includes a comparator and an indicator. The comparator has a power signal input, a threshold signal input, and a comparison result output, and is configured to compare the power signal on the power signal input with a threshold on the threshold signal input to present a comparison result signal on the comparison result output. The indicator has a threshold violation output and a comparison input that receives the comparison result signal from the comparator. The indicator presents a threshold violation signal on the threshold violation output when the comparison result signal indicates that the power signal has violated the threshold.
摘要翻译： 用于测量来自电源的功率信号的稳定性的系统包括阈值违规检测器。 阈值违规检测器包括比较器和指示器。 比较器具有功率信号输入，阈值信号输入和比较结果输出，并且被配置为将功率信号输入上的功率信号与阈值信号输入上的阈值进行比较，以在比较结果上呈现比较结果信号 输出。 指示器具有阈值违反输出和比较输入，其从比较器接收比较结果信号。 当比较结果信号指示电源信号已经违反阈值时，指示器在阈值违反输出上呈现阈值违反信号。
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8.发明授权公开(公告)号：US06493254B1
公开(公告)日：2002-12-10
申请号：US09896348
申请日：2001-06-28
IPC分类号： G11C1140
CPC分类号： G11C11/412
摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.
摘要翻译： 本发明的实施例涉及具有重负载位线的存储器电路，并且其中读取访问或传输晶体管中的漏电流的影响减小或漏电流减小。
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公开(公告)号：US06388940B1
公开(公告)日：2002-05-14
申请号：US09672177
申请日：2000-09-27
IPC分类号： G11C800
CPC分类号： G11C7/12 , G11C11/419
摘要： A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.
摘要翻译： 一种新颖的电路技术，用于减小通过大寄存器堆的读路径的漏电流，其中在栅极读取晶体管和局部位线之间的临界传输晶体管上施加负栅极 - 源极电压，使得当单元处于第一 状态，来自单元读取晶体管的动态节点的漏电流减小。 减小的漏电流增加了读操作的鲁棒性和性能。
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公开(公告)号：US06919737B2
公开(公告)日：2005-07-19
申请号：US10010737
申请日：2001-12-07
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018521
摘要： A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.
摘要翻译： 描述电压电平转换器和将第一逻辑电压电平转换到第二逻辑电压电平的方法。 在一个实施例中，电压电平转换器将连接到第一电源电压的第一逻辑单元连接到与第二电源电压连接的第二逻辑单元。 电压电平转换器包括连接到第二电源电压的至少一个晶体管。 所述至少一个晶体管具有其绝对值大于或等于所述第二电源电压和所述第一电源电压之间的差的绝对值的阈值电压。 在替代实施例中，用于将第一逻辑电压电平转换为第二逻辑电压电平的方法包括从具有在第一电压电平和第二电压电平之间的输出电压摆幅的逻辑单元传输逻辑信号，接收逻辑信号 在具有上拉晶体管的逻辑电路和在第三电压电平和第四电压电平之间的输出电压摆幅，并且当所述逻辑信号具有略大于所述第三电压 电平和第一电压电平。
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