公开(公告)号：US20190158606A1

公开(公告)日：2019-05-23

申请号：US16235137

申请日：2018-12-28

Applicant: FRANCESC GUIM BERNAT ,  PATRICK BOHAN ,  KSHITIJ ARUN DOSHI ,  BRINDA GANESH ,  ANDREW J. HERDRICH ,  MONICA KENGUVA ,  KARTHIK KUMAR ,  PATRICK G. KUTCH ,  FELIPE PASTOR BENEYTO ,  RASHMIN PATEL ,  SURAJ PRABHAKARAN ,  NED M. SMITH ,  PETAR TORRE ,  ALEXANDER VUL

Inventor： FRANCESC GUIM BERNAT ,  PATRICK BOHAN ,  KSHITIJ ARUN DOSHI ,  BRINDA GANESH ,  ANDREW J. HERDRICH ,  MONICA KENGUVA ,  KARTHIK KUMAR ,  PATRICK G. KUTCH ,  FELIPE PASTOR BENEYTO ,  RASHMIN PATEL ,  SURAJ PRABHAKARAN ,  NED M. SMITH ,  PETAR TORRE ,  ALEXANDER VUL

IPC: H04L29/08 ,  H04L12/26 ,  H04L12/911 ,  H04L12/24

Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes. In a specific example, a technique for service migration includes: identifying a service operated with computing resources in an edge computing system, involving computing capabilities for a connected edge device with an identified service level; identifying a mobility condition for the service, based on a change in network connectivity with the connected edge device; and performing a migration of the service to another edge computing system based on the identified mobility condition, to enable the service to be continued at the second edge computing apparatus to provide computing capabilities for the connected edge device with the identified service level.

公开(公告)号：US20210021594A1

公开(公告)日：2021-01-21

申请号：US17032696

申请日：2020-09-25

Applicant: Francesc Guim Bernat ,  Ned M. Smith ,  Kshitij Arun Doshi ,  Suraj Prabhakaran ,  Brinda Ganesh

Inventor： Francesc Guim Bernat ,  Ned M. Smith ,  Kshitij Arun Doshi ,  Suraj Prabhakaran ,  Brinda Ganesh

IPC: H04L29/06

Abstract: Various aspects of methods, systems, and use cases for biometric security for edge platform management. An edge cloud system to implement biometric security for edge platform management comprises a biometric sensor; and an edge node in an edge network, the edge node to: receive a request to access a feature of the edge node, the request originating from an entity, wherein the request comprises an entity identifier and a feature identifier; receive from the biometric sensor, biometric data of the entity; authenticate the entity using the biometric data; and in response to authenticating the entity using the biometric data, grant access to the feature based on a crosscheck to an access control list that includes entity identifiers correlated to feature identifiers, using the received entity identifier and the received feature identifier.

公开(公告)号：US20080276240A1

公开(公告)日：2008-11-06

申请号：US11744546

申请日：2007-05-04

Applicant: Brinda Ganesh ,  Xiaowei Shen ,  Jessica Hui-Chun Tseng

Inventor： Brinda Ganesh ,  Xiaowei Shen ,  Jessica Hui-Chun Tseng

IPC: G06F9/46

CPC classification number: G06F13/4239 ,  G06F13/1626 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system includes a deterministic system, and a controller electrically coupled to the deterministic system via a link, wherein the controller comprises a transaction scheduling mechanism that allows data responses from the deterministic system, corresponding to requests issued from the controller, to be returned out of order.

Abstract translation: 一种系统包括确定性系统和经由链路电耦合到确定性系统的控制器，其中所述控制器包括事务调度机制，其允许来自所述确定性系统的数据响应对应于从所述控制器发出的请求返回到 订购。

公开(公告)号：US09021482B2

公开(公告)日：2015-04-28

申请号：US11744546

申请日：2007-05-04

Applicant: Brinda Ganesh ,  Xiaowei Shen ,  Jessica Hui-Chun Tseng

Inventor： Brinda Ganesh ,  Xiaowei Shen ,  Jessica Hui-Chun Tseng

IPC: G06F9/46 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4239 ,  G06F13/1626 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system includes a deterministic system, and a controller electrically coupled to the deterministic system via a link, wherein the controller comprises a transaction scheduling mechanism that allows data responses from the deterministic system, corresponding to requests issued from the controller, to be returned out of order.

Abstract translation: 一种系统包括确定性系统和经由链路电耦合到确定性系统的控制器，其中所述控制器包括事务调度机制，其允许来自所述确定性系统的数据响应对应于从所述控制器发出的请求返回到 订购。

公开(公告)号：US20140189239A1

公开(公告)日：2014-07-03

申请号：US13729579

申请日：2012-12-28

Applicant: Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract translation: 一方面的处理器包括多个逻辑处理器，每个逻辑处理器具有一个或多个相应的较低级别的高速缓存。 共享的较高级缓存由多个逻辑处理器共享。 共享的较高级缓存包括用于每个逻辑处理器的分布式缓存片。 处理器包括用于将对应逻辑处理器的一个或多个较低级别高速缓存中的访问指向与对应于逻辑处理器的虚拟集群中的分布式高速缓存片段的子集的逻辑。 还公开了其他处理器，方法和系统。

公开(公告)号：US20190227979A1

公开(公告)日：2019-07-25

申请号：US16369220

申请日：2019-03-29

Applicant: Brinda Ganesh ,  Yen-Cheng Liu ,  Swadesh Choudhary ,  Tejpal Singh ,  Pradeep Prabhakaran ,  Monam Agarwal

Inventor： Brinda Ganesh ,  Yen-Cheng Liu ,  Swadesh Choudhary ,  Tejpal Singh ,  Pradeep Prabhakaran ,  Monam Agarwal

IPC: G06F15/173 ,  G06F13/40 ,  H01L21/768 ,  H01L25/065

Abstract: In one embodiment, a system on chip includes: a plurality of intellectual property (IP) agents formed on a semiconductor die; a mesh interconnect formed on the semiconductor die to couple the plurality of IP agents, and a plurality of mesh stops each to couple one or more of the plurality of IP agents to the mesh interconnect. The mesh interconnect may be formed of a plurality of rows each having one of a plurality of horizontal interconnects and a plurality of columns each having one of a plurality of vertical interconnects;, where at least one of the plurality of rows includes an asymmetrical number of mesh stops. Other embodiments are described and claimed.