公开(公告)号：US20240232078A1

公开(公告)日：2024-07-11

申请号：US18399553

申请日：2023-12-28

Applicant: Andrew J. HERDRICH ,  Priya AUTEE ,  Abhishek KHADE ,  Patrick LU ,  Edwin VERPLANKE ,  Vivekananthan SANJEEPAN

Inventor： Andrew J. HERDRICH ,  Priya AUTEE ,  Abhishek KHADE ,  Patrick LU ,  Edwin VERPLANKE ,  Vivekananthan SANJEEPAN

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/681

Abstract: Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.

公开(公告)号：US20170094377A1

公开(公告)日：2017-03-30

申请号：US14866567

申请日：2015-09-25

Applicant: Andrew J. Herdrich ,  Patrick L. Connor ,  Dinesh Kumar ,  Alexander W. Min ,  Daniel J. Dahle ,  Kapil Sood ,  Jeffrey A. Shaw ,  Edwin Verplanke ,  Scott P. Dubal ,  James R. Hearn

Inventor： Andrew J. Herdrich ,  Patrick L. Connor ,  Dinesh Kumar ,  Alexander W. Min ,  Daniel J. Dahle ,  Kapil Sood ,  Jeffrey A. Shaw ,  Edwin Verplanke ,  Scott P. Dubal ,  James R. Hearn

IPC: H04Q9/02 ,  H04L12/26 ,  H04L12/24

CPC classification number: H04Q9/02 ,  H04L41/5009 ,  H04L41/5019 ,  H04L43/08 ,  H04L43/10

Abstract: Devices and techniques for out-of-band platform tuning and configuration are described herein. A device can include a telemetry interface to a telemetry collection system and a network interface to network adapter hardware. The device can receive platform telemetry metrics from the telemetry collection system, and network adapter silicon hardware statistics over the network interface, to gather collected statistics. The device can apply a heuristic algorithm using the collected statistics to determine processing core workloads generated by operation of a plurality of software systems communicatively coupled to the device. The device can provide a reconfiguration message to instruct at least one software system to switch operations to a different processing core, responsive to detecting an overload state on at least one processing core, based on the processing core workloads. Other embodiments are also described.

公开(公告)号：US20180095880A1

公开(公告)日：2018-04-05

申请号：US15282483

申请日：2016-09-30

Applicant: Kshitij A. Doshi ,  Namakkal N. Venkatesan ,  Ren Wang ,  Andrew J. Herdrich

Inventor： Kshitij A. Doshi ,  Namakkal N. Venkatesan ,  Ren Wang ,  Andrew J. Herdrich

IPC: G06F12/0811 ,  G06F9/30

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F12/128 ,  G06F2212/283 ,  Y02D10/13

Abstract: Processors and methods implementing a machine instruction to perform cache line demotion on multiple cache lines to enable efficient sharing of cache lines between processor cores. One general aspect includes a processor comprising: a plurality of hardware processor cores, where each of the hardware processor cores to include a first cache. The processor also includes a second cache, communicatively coupled to and shared by the plurality of hardware processor cores. The processor to support a first machine instruction, the first machine instruction to include a vector register operand identifying a vector register which contains a plurality of data elements each used to identify a cache line. An execution of the first machine instruction by one of the plurality of hardware processor cores to cause a plurality of identified cache lines to be demoted, such that the demoted cache lines are moved from the first cache to the second cache.

公开(公告)号：US20170289068A1

公开(公告)日：2017-10-05

申请号：US15088910

申请日：2016-04-01

Applicant: Stephen T. Palermo ,  Iosif Gasparakis ,  Scott P. Dubal ,  Kapil Sood ,  Trevor Cooper ,  Jr-Shian Tsai ,  Jesse C. Brandeburg ,  Andrew J. Herdrich ,  Edwin Verplanke

Inventor： Stephen T. Palermo ,  Iosif Gasparakis ,  Scott P. Dubal ,  Kapil Sood ,  Trevor Cooper ,  Jr-Shian Tsai ,  Jesse C. Brandeburg ,  Andrew J. Herdrich ,  Edwin Verplanke

IPC: H04L12/861 ,  H04L12/931 ,  G06F15/173 ,  H04L12/715

CPC classification number: H04L49/9047 ,  G06F9/45558 ,  G06F15/17331 ,  G06F2009/45595 ,  H04L45/64 ,  H04L49/70

Abstract: Methods and apparatus for accelerating VM-to-VM Network Traffic using CPU cache. A virtual queue manager (VQM) manages data that is to be kept in VM-VM shared data buffers in CPU cache. The VQM stores a list of VM-VM allow entries identifying data transfers between VMs that may use VM-VM cache “fast-path” forwarding. Packets are sent from VMs to the VQM for forwarding to destination VMs. Indicia in the packets (e.g., in a tag or header) is inspected to determine whether a packet is to be forwarded via a VM-VM cache fast path or be forwarded via a virtual switch. The VQM determines the VM data already in the CPU cache domain while concurrently coordinating with the data to and from the external shared memory, and also ensures data coherency between data kept in cache and that which is kept in shared memory.

公开(公告)号：US09769050B2

公开(公告)日：2017-09-19

申请号：US14581595

申请日：2014-12-23

Applicant: Andrew J. Herdrich ,  Patrick Connor ,  Dinesh Kumar ,  Alexander W. Min ,  Ravishankar Iyer ,  Daniel J. Dahle ,  Kapil Sood ,  Jeffrey B. Shaw

Inventor： Andrew J. Herdrich ,  Patrick Connor ,  Dinesh Kumar ,  Alexander W. Min ,  Ravishankar Iyer ,  Daniel J. Dahle ,  Kapil Sood ,  Jeffrey B. Shaw

IPC: G06F15/173 ,  H04L12/26 ,  H04L12/24 ,  G06F12/084 ,  G06F12/0811

CPC classification number: H04L43/50 ,  G06F12/0811 ,  G06F12/084 ,  G06F2212/152 ,  G06F2212/601 ,  H04L41/0896 ,  H04L41/5009 ,  H04L41/5025 ,  H04L41/5035 ,  H04L41/5096 ,  H04L43/16

Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with end-to-end datacenter performance control. In various embodiments, an apparatus for computing may receive a datacenter performance target, determine an end-to-end datacenter performance level based at least in part on quality of service data collected from a plurality of nodes, and send a mitigation command based at least in part on a result of a comparison of the end-to-end datacenter performance level determined to the datacenter performance target. In various embodiments, the apparatus for computing may include one or more processors, a memory, a datacenter performance monitor to receive a datacenter performance target corresponding to a service level agreement, and a mitigation module to send a mitigation command based at least in part on a result of a comparison of an end-to-end datacenter performance level to a datacenter performance target.

公开(公告)号：US20160246652A1

公开(公告)日：2016-08-25

申请号：US14627912

申请日：2015-02-20

Applicant: ANDREW J. HERDRICH ,  KAPIL SOOD ,  NRUPAL R. JANI ,  DAVID J. HARRIMAN ,  MESUT A. ERGIN ,  SCOTT P. DUBAL ,  RAVISHANKAR IYER

Inventor： ANDREW J. HERDRICH ,  KAPIL SOOD ,  NRUPAL R. JANI ,  DAVID J. HARRIMAN ,  MESUT A. ERGIN ,  SCOTT P. DUBAL ,  RAVISHANKAR IYER

IPC: G06F9/50

CPC classification number: G06F9/5077

Abstract: Examples may include techniques to coordinate the sharing of resources among virtual elements, including service chains, supported by a shared pool of configurable computing resources based on relative priority among the virtual element and service chains. Information including indications of the performance of the service chains and also the relative priority of the service chains may be received. The resource allocation of portions of the shared pool of configurable computing resources supporting the service chains can be adjusted based on the received performance and priority information.

Abstract translation: 示例可以包括基于虚拟元素和服务链之间的相对优先级来协调由可配置计算资源的共享池支持的虚拟元素（包括服务链）之间的资源共享的技术。 可以接收包括服务链表现的指示以及服务链的相对优先级的信息。 可以基于接收到的性能和优先级信息来调整支持服务链的可配置计算资源的共享池的部分的资源分配。

公开(公告)号：US20140281457A1

公开(公告)日：2014-09-18

申请号：US13854001

申请日：2013-03-29

Applicant: Elierzer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V. Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russel J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

Inventor： Elierzer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V. Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russel J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

IPC: G06F9/44

CPC classification number: G06F9/4401 ,  G06F9/45558 ,  G06F9/5077 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/36

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract translation: 描述异构处理器架构和启动异构处理器的方法。 根据一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 以及一个包装单元，用于启用自举处理器。 引导处理器初始化同构物理处理器内核，而异构处理器将均匀处理器的外观呈现给系统固件界面。

公开(公告)号：US20140189704A1

公开(公告)日：2014-07-03

申请号：US13730539

申请日：2012-12-28

Applicant: Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/50

CPC classification number: G06F9/5044 ,  G06F9/45533 ,  G06F9/5077 ,  G06F9/5094 ,  G06F15/80 ,  Y02D10/22

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同 虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心组内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行 从第一组或第二组物理处理器到第一虚拟处理器。

公开(公告)号：US20140095691A1

公开(公告)日：2014-04-03

申请号：US13630545

申请日：2012-09-28

Applicant: Mrittika Ganguli ,  Muthuvel M. I. ,  Ananth S. Narayan ,  Jaideep Moses ,  Andrew J. Herdrich ,  Rahul Khanna

Inventor： Mrittika Ganguli ,  Muthuvel M. I. ,  Ananth S. Narayan ,  Jaideep Moses ,  Andrew J. Herdrich ,  Rahul Khanna

IPC: H04L12/24

CPC classification number: H04L41/50 ,  H04L41/145 ,  H04L41/5009 ,  H04L41/5025

Abstract: In accordance with some embodiments, a cloud service provider may operate a data center in a way that dynamically reallocates resources across nodes within the data center based on both utilization and service level agreements. In other words, the allocation of resources may be adjusted dynamically based on current conditions. The current conditions in the data center may be a function of the nature of all the current workloads. Instead of simply managing the workloads in a way to increase overall execution efficiency, the data center instead may manage the workload to achieve quality of service requirements for particular workloads according to service level agreements.

Abstract translation: 根据一些实施例，云服务提供商可以以基于利用率和服务水平协议来动态地重新分配数据中心内的节点之间的资源的方式来操作数据中心。 换句话说，资源分配可以根据当前条件动态调整。 数据中心当前的状况可能是所有当前工作负载的性质的函数。 而不是简单地以提高总体执行效率的方式管理工作负载，而是根据服务级别协议，数据中心可以管理工作负载以实现特定工作负载的服务质量要求。

公开(公告)号：US20190158606A1

公开(公告)日：2019-05-23

申请号：US16235137

申请日：2018-12-28

Applicant: FRANCESC GUIM BERNAT ,  PATRICK BOHAN ,  KSHITIJ ARUN DOSHI ,  BRINDA GANESH ,  ANDREW J. HERDRICH ,  MONICA KENGUVA ,  KARTHIK KUMAR ,  PATRICK G. KUTCH ,  FELIPE PASTOR BENEYTO ,  RASHMIN PATEL ,  SURAJ PRABHAKARAN ,  NED M. SMITH ,  PETAR TORRE ,  ALEXANDER VUL

Inventor： FRANCESC GUIM BERNAT ,  PATRICK BOHAN ,  KSHITIJ ARUN DOSHI ,  BRINDA GANESH ,  ANDREW J. HERDRICH ,  MONICA KENGUVA ,  KARTHIK KUMAR ,  PATRICK G. KUTCH ,  FELIPE PASTOR BENEYTO ,  RASHMIN PATEL ,  SURAJ PRABHAKARAN ,  NED M. SMITH ,  PETAR TORRE ,  ALEXANDER VUL

IPC: H04L29/08 ,  H04L12/26 ,  H04L12/911 ,  H04L12/24

Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes. In a specific example, a technique for service migration includes: identifying a service operated with computing resources in an edge computing system, involving computing capabilities for a connected edge device with an identified service level; identifying a mobility condition for the service, based on a change in network connectivity with the connected edge device; and performing a migration of the service to another edge computing system based on the identified mobility condition, to enable the service to be continued at the second edge computing apparatus to provide computing capabilities for the connected edge device with the identified service level.