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17 条记录 (耗时 0.014 秒)

    SEMICONDUCTOR DEVICE, MAGNETIC MEMORY DEVICE, AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE, MAGNETIC MEMORY DEVICE, AND METHOD OF FABRICATING THE SAME 有权
    半导体器件，磁存储器件及其制造方法

    公开(公告)号：US20150311433A1

    公开(公告)日：2015-10-29

    申请号：US14606157

    申请日：2015-01-27

    申请人： Byoungjae BAE ,  Jongchul PARK ,  Shin KWON ,  Inho KIM ,  Changwoo SUN

    发明人： Byoungjae BAE ,  Jongchul PARK ,  Shin KWON ,  Inho KIM ,  Changwoo SUN

    IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/08

    CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

    摘要： A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.

    摘要翻译： 一种制造半导体器件的方法包括在衬底上形成导电柱，在导电柱之间依次形成牺牲层和模制结构，在模制结构上形成导电层，使得导电层连接到导电柱上， 去除牺牲层以形成气隙，去除模制结构以形成扩张空气间隙，并且图案化导电层以打开膨胀的气隙。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10164170B2

    公开(公告)日：2018-12-25

    申请号：US15622064

    申请日：2017-06-13

    申请人： Kiseok Suh ,  Byoungjae Bae ,  Gwanhyeob Koh ,  Yoonjong Song ,  Kilho Lee

    发明人： Kiseok Suh ,  Byoungjae Bae ,  Gwanhyeob Koh ,  Yoonjong Song ,  Kilho Lee

    IPC分类号： H01L43/02 ,  H01L43/08 ,  H01L27/22

    摘要： A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180159023A1

    公开(公告)日：2018-06-07

    申请号：US15622064

    申请日：2017-06-13

    申请人： Kiseok SUH ,  BYOUNGJAE BAE ,  GWANHYEOB KOH ,  YOONJONG SONG ,  KILHO LEE

    发明人： Kiseok SUH ,  BYOUNGJAE BAE ,  GWANHYEOB KOH ,  YOONJONG SONG ,  KILHO LEE

    IPC分类号： H01L43/02 ,  H01L43/08 ,  H01L27/22

    CPC分类号： H01L43/02 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

    摘要： A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

    MAGNETIC MEMORY DEVICES
    8.
    发明申请
    MAGNETIC MEMORY DEVICES 有权
    磁记忆装置

    公开(公告)号：US20150287907A1

    公开(公告)日：2015-10-08

    申请号：US14567932

    申请日：2014-12-11

    申请人： Jongchul PARK ,  Byoungjae BAE ,  Shin-Jae KANG ,  Eunsun NOH ,  Kyung Rae BYUN

    发明人： Jongchul PARK ,  Byoungjae BAE ,  Shin-Jae KANG ,  Eunsun NOH ,  Kyung Rae BYUN

    IPC分类号： H01L43/08 ,  H01L43/02

    CPC分类号： H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

    摘要： Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns.

    摘要翻译： 磁存储器件包括在基板上彼此间隔开的多个第一磁性图案，第一磁性图案之间的第一绝缘图案，以限定第一磁性图案，以及覆盖第一磁性图案的隧道势垒层和 第一绝缘图案。 第一绝缘图案包括第一磁性元件，第一磁性元件与构成第一磁性图案的第二磁性元件相同。

    MAGNETIC MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    9.
    发明申请
    MAGNETIC MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    磁记忆体装置及其制造方法

    公开(公告)号：US20140117477A1

    公开(公告)日：2014-05-01

    申请号：US14067108

    申请日：2013-10-30

    申请人： Jongchul PARK ,  Sechung OH ,  Byoungjae BAE ,  Daeeun JEONG

    发明人： Jongchul PARK ,  Sechung OH ,  Byoungjae BAE ,  Daeeun JEONG

    IPC分类号： H01L43/02

    CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/228

    摘要： Magnetic memory devices, and methods of fabricating the same, include lower magnetic patterns arranged along first and second directions orthogonal to each other on a substrate, an upper magnetic layer covering at least two of the lower magnetic patterns arranged along the first direction and at least two of the lower magnetic patterns arranged along the second direction, and a tunnel barrier layer the lower magnetic patterns and the upper magnetic layer.

    摘要翻译： 磁存储器件及其制造方法包括沿着衬底上彼此正交的第一和第二方向布置的较低磁性图案，覆盖沿着第一方向布置的至少两个下部磁性图案的上部磁性层，并且至少 沿着第二方向布置的两个下磁性图案，以及隧道势垒层，下部磁图案和上部磁性层。

    Methods of forming variable-resistance memory devices and devices formed thereby
    10.
    发明授权
    Methods of forming variable-resistance memory devices and devices formed thereby 有权
    形成可变电阻存储器件和由此形成的器件的方法

    公开(公告)号：US08598010B2

    公开(公告)日：2013-12-03

    申请号：US13090553

    申请日：2011-04-20

    申请人： Heung Jin Joo ,  JaeHee Oh ,  Byoungjae Bae ,  Myung Jin Kang

    发明人： Heung Jin Joo ,  JaeHee Oh ,  Byoungjae Bae ,  Myung Jin Kang

    IPC分类号： H01L21/02

    CPC分类号： H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/1683

    摘要： Methods of forming a variable-resistance memory device include patterning an interlayer dielectric layer to define an opening therein that exposes a bottom electrode of a variable-resistance memory cell, on a memory cell region of a substrate (e.g., semiconductor substrate). These methods further include depositing a layer of variable-resistance material (e.g., phase-changeable material) onto the exposed bottom electrode in the opening and onto a first portion of the interlayer dielectric layer extending opposite a peripheral circuit region of the substrate. The layer of variable-resistance material and the first portion of the interlayer dielectric layer are then selectively etched in sequence to define a recess in the interlayer dielectric layer. The layer of variable-resistance material and the interlayer dielectric layer are then planarized to define a variable-resistance pattern within the opening.

    摘要翻译： 形成可变电阻存储器件的方法包括图案化层间电介质层以限定其中可露出可变电阻存储单元的底部电极的开口，在衬底（例如，半导体衬底）的存储单元区域上。 这些方法还包括在开口中的暴露的底部电极上沉​​积可变电阻材料层（例如，相变材料），并且延伸到与衬底的外围电路区域相对延伸的层间电介质层的第一部分上。 然后依次选择性地蚀刻可变电阻材料层和层间电介质层的第一部分，以在层间介质层中限定凹陷。 然后将可变电阻材料层和层间电介质层平坦化，以在开口内限定可变电阻图案。