公开(公告)号：US09502643B2

公开(公告)日：2016-11-22

申请号：US14606157

申请日：2015-01-27

Applicant: Byoungjae Bae ,  Jongchul Park ,  Shin Kwon ,  Inho Kim ,  Changwoo Sun

Inventor： Byoungjae Bae ,  Jongchul Park ,  Shin Kwon ,  Inho Kim ,  Changwoo Sun

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/08

Abstract: A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成导电柱，在导电柱之间依次形成牺牲层和模制结构，在模制结构上形成导电层，使得导电层连接到导电柱上， 去除牺牲层以形成气隙，去除模制结构以形成扩张空气间隙，并且图案化导电层以打开膨胀的气隙。

公开(公告)号：US08619484B2

公开(公告)日：2013-12-31

申请号：US13228102

申请日：2011-09-08

Applicant: Jong Hyoung Lim ,  Sang Seok Kang ,  Hyung Shin Kwon

Inventor： Jong Hyoung Lim ,  Sang Seok Kang ,  Hyung Shin Kwon

IPC: G11C7/02

CPC classification number: G11C7/12

Abstract: A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

Abstract translation: 半导体器件包括位线，互补位线，被配置为感测和放大位线和互补位线之间的电压差的读出放大器，以及电容调整电路，配置为调整互补位线的负载电容 响应于多个控制信号。

公开(公告)号：US08558347B2

公开(公告)日：2013-10-15

申请号：US13780622

申请日：2013-02-28

Applicant: Hyung-Shin Kwon ,  Hyung-Dong Kim

Inventor： Hyung-Shin Kwon ,  Hyung-Dong Kim

IPC: H01L21/02

CPC classification number: H01L28/60 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

Abstract translation: 半导体器件可以包括取决于衬底上的位置的具有不同高度的下电极。 提供了与具有相对较大高度的下电极接触的支撑层图案。 支撑层图案设置在用于支撑下电极的下电极之间。 电介质层设置在下电极和支撑层图案上。 在电介质层上形成上电极，具有平坦的上表面。 在上电极上设置金属间介电层。 形成穿过金属间介电层并与上电极接触的金属接触。 金属接触件的底部部分形成在具有较小高度的下部电极下方的部分。 该设备具有较高的可靠性。

公开(公告)号：US20100019372A1

公开(公告)日：2010-01-28

申请号：US12507979

申请日：2009-07-23

Applicant: Han-Shin YOUN ,  Young-Shin Kwon

Inventor： Han-Shin YOUN ,  Young-Shin Kwon

IPC: H01L23/498 ,  H01L23/34

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

Abstract translation: 半导体器件封装包括半导体芯片，其包括导电焊盘，其上安装半导体芯片并具有第一厚度的裸片焊盘，引线图案包括邻近于芯片焊盘的边缘设置的第一部分，并具有第一厚度 和具有大于第一厚度的第二厚度的第二部分，设置在芯片焊盘和引线图案上并包括形成在其底表面上的凹槽的散热部件和设置成将导电焊盘电连接到 引线图案对应于导电焊盘并部分插入凹槽中。

公开(公告)号：US20090315130A1

公开(公告)日：2009-12-24

申请号：US10915334

申请日：2004-08-11

Applicant: Young-Hoon Ro ,  Young-Shin Kwon ,  Seung-Kon Mok

Inventor： Young-Hoon Ro ,  Young-Shin Kwon ,  Seung-Kon Mok

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L2224/48091 ,  H04N5/2253 ,  H04N5/2257 ,  H01L2924/00014

Abstract: A solid-state imaging apparatus and method for manufacturing the imaging apparatus. A solid-state imaging apparatus with reduced thickness and/or mounting area by forming an aperture in a board and placing a solid-state semiconductor imaging chip, an image processing semiconductor chip, and/or a combination imaging/processing chip within the aperture.

Abstract translation: 一种用于制造成像装置的固态成像装置和方法。 一种具有减小厚度和/或安装面积的固态成像装置，其通过在板中形成孔并将固态半导体成像芯片，图像处理半导体芯片和/或组合成像/处理芯片放置在孔内。

公开(公告)号：US20070293030A1

公开(公告)日：2007-12-20

申请号：US11845707

申请日：2007-08-27

Applicant: Hyung-Shin KWON ,  Joon-Yong JOO ,  Kwang-Ok KOH ,  Sung-Bong KIM

Inventor： Hyung-Shin KWON ,  Joon-Yong JOO ,  Kwang-Ok KOH ,  Sung-Bong KIM

IPC: H01L21/3205

CPC classification number: H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.

Abstract translation: 本发明提供一种具有硅化物薄膜的半导体器件及其形成方法。 半导体器件包括形成在半导体衬底的有源区上的栅极绝缘层。 在栅极绝缘层上形成栅电极。 在与栅电极相邻的有源区中形成杂质区。 诸如硅化钴薄膜的硅化物薄膜在杂质区域中形成为小于约200埃的厚度。

公开(公告)号：US07172944B2

公开(公告)日：2007-02-06

申请号：US11282156

申请日：2005-11-18

Applicant: Hyung-Shin Kwon

Inventor： Hyung-Shin Kwon

IPC: H01L21/336

CPC classification number: H01L29/665 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/0266 ,  H01L29/41775 ,  H01L29/4933 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628

Abstract: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided. Further, the method includes defining an active region a semiconductor substrate, forming a gate electrode crossing over the active region, sequentially stacking first and second insulating layer patterns an active region adjacent to opposite sides of the gate electrode, forming a silicon epitaxial layer on the active region to be adjacent to edges of the first and second insulating layer patterns, and siliciding at least a part of the silicon epitaxial layer. The edge of the first insulating layer pattern contacting the active region is protruded from the edge of the second insulating layer pattern, and the silicon epitaxial layer covers the protruded edge of the first insulating layer pattern.

Abstract translation: 本发明提供一种具有升高的源极/漏极的半导体器件及其制造方法。 在半导体器件中，在半导体衬底的预定区域限定有源区，并且形成栅电极以跨越有源区。 第一绝缘层图案和第二绝缘层图案依次层叠在栅电极的侧壁上，并且在有源区上形成与第一绝缘层图案和第二绝缘层图案的边缘相邻的硅外延层。 第一绝缘层图案的边缘从第二绝缘层图案的边缘突出以被预定区域被硅化的硅外延层覆盖。 此外，该方法包括限定有源区域，形成跨越有源区域的栅电极的半导体衬底，顺序地将第一和第二绝缘层图案堆叠在与栅电极的相对侧相邻的有源区域上，在该栅极电极上形成硅外延层 有源区域与第一和第二绝缘层图案的边缘相邻，并且硅化硅外延层的至少一部分。 与有源区接触的第一绝缘层图案的边缘从第二绝缘层图案的边缘突出，并且硅外延层覆盖第一绝缘层图案的突出边缘。

公开(公告)号：US08278154B2

公开(公告)日：2012-10-02

申请号：US13278857

申请日：2011-10-21

Applicant: Han-Shin Youn ,  Young-Shin Kwon

Inventor： Han-Shin Youn ,  Young-Shin Kwon

IPC: H01L21/00 ,  H01L23/495

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

Abstract translation: 半导体器件封装包括半导体芯片，其包括导电焊盘，其上安装半导体芯片并具有第一厚度的裸片焊盘，引线图案包括邻近于芯片焊盘的边缘设置的第一部分，并具有第一厚度 和具有大于第一厚度的第二厚度的第二部分，设置在芯片焊盘和引线图案上并包括形成在其底表面上的凹槽的散热部件和设置成将导电焊盘电连接到 引线图案对应于导电焊盘并部分插入凹槽中。

公开(公告)号：US20120063251A1

公开(公告)日：2012-03-15

申请号：US13228102

申请日：2011-09-08

Applicant: Jong Hyoung LIM ,  Sang Seok Kang ,  Hyung Shin Kwon

Inventor： Jong Hyoung LIM ,  Sang Seok Kang ,  Hyung Shin Kwon

IPC: G11C7/06

CPC classification number: G11C7/12

Abstract: A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

Abstract translation: 半导体器件包括位线，互补位线，被配置为感测和放大位线和互补位线之间的电压差的读出放大器，以及电容调整电路，配置为调整互补位线的负载电容 响应于多个控制信号。

公开(公告)号：US20120052648A1

公开(公告)日：2012-03-01

申请号：US13221099

申请日：2011-08-30

Applicant: Hyung-Shin Kwon ,  Hyung-Dong Kim

Inventor： Hyung-Shin Kwon ,  Hyung-Dong Kim

IPC: H01L21/02

CPC classification number: H01L28/60 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

Abstract translation: 半导体器件可以包括取决于衬底上的位置的具有不同高度的下电极。 提供了与具有相对较大高度的下电极接触的支撑层图案。 支撑层图案设置在用于支撑下电极的下电极之间。 电介质层设置在下电极和支撑层图案上。 在电介质层上形成上电极，具有平坦的上表面。 在上电极上设置金属间介电层。 形成穿过金属间介电层并与上电极接触的金属接触。 金属接触件的底部部分形成在具有较小高度的下部电极下方的部分。 该设备具有较高的可靠性。