公开(公告)号：US10115893B2

公开(公告)日：2018-10-30

申请号：US15606136

申请日：2017-05-26

Applicant: Jongchul Park ,  Sang-Kuk Kim

Inventor： Jongchul Park ,  Sang-Kuk Kim

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.

公开(公告)号：US20170263675A1

公开(公告)日：2017-09-14

申请号：US15415828

申请日：2017-01-25

Applicant: JONGCHUL PARK

Inventor： JONGCHUL PARK

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method for manufacturing a magnetic memory device includes forming a magnetic tunnel junction layer that includes a first magnetic layer, a tunnel barrier layer, and a second magnetic layer sequentially stacked on a substrate. First line mask patterns are formed extending in a first direction and spaced apart from each other in a second direction crossing the first direction. The magnetic tunnel junction layer is etched by a first ion-beam etch process using the first line mask patterns as an etch mask to form preliminary magnetic tunnel junctions. Second line mask patterns are formed extending in the second direction and spaced apart from each other in the first direction. The preliminary magnetic tunnel junctions are etched by a second ion-beam process using the second line mask patterns as an etch mask to form magnetic tunnel junctions.

公开(公告)号：US20170062709A1

公开(公告)日：2017-03-02

申请号：US15180843

申请日：2016-06-13

Applicant: Sang-Kuk KIM ,  Jong-Kyu KIM ,  Jongchul PARK ,  Inho KIM ,  Gwang-Hyun BAEK ,  Jung-Ik OH

Inventor： Sang-Kuk KIM ,  Jong-Kyu KIM ,  Jongchul PARK ,  Inho KIM ,  Gwang-Hyun BAEK ,  Jung-Ik OH

IPC: H01L43/12 ,  H01L43/10 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method for forming a pattern, the method including forming an etch target layer on a substrate; patterning the etch target layer to form patterns; and performing a pre-oxidation trim process a plurality of times, the pre-oxidation trim process including performing an oxidation process to form an insulating layer on a sidewall of each of the patterns; and performing a sputter etch process to remove at least a portion of the insulating layer.

Abstract translation: 一种用于形成图案的方法，所述方法包括在基底上形成蚀刻目标层; 图案化蚀刻目标层以形成图案; 并且进行预氧化修饰过程多次，所述预氧化修剪处理包括进行氧化处理以在每个图案的侧壁上形成绝缘层; 以及执行溅射蚀刻工艺以去除所述绝缘层的至少一部分。

公开(公告)号：US20170053965A1

公开(公告)日：2017-02-23

申请号：US15158981

申请日：2016-05-19

Applicant: GWANG-HYUN BAEK ,  lnho KIM ,  Jong-Kyu KIM ,  Jongchul PARK ,  Jung-lk OH

Inventor： GWANG-HYUN BAEK ,  lnho KIM ,  Jong-Kyu KIM ,  Jongchul PARK ,  Jung-lk OH

IPC: H01L27/22 ,  H01L43/08 ,  H01L23/528 ,  H01L43/12 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L23/528 ,  H01L27/226 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device including a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a magnetic tunnel junction pattern on the first conductive pattern, and a contact plug coupled to the second conductive pattern may be provided. Further, a method of fabricating the memory device also may be provided.

Abstract translation: 一种存储器件，包括衬底，衬底上的绝缘层，所述绝缘层包括具有第一顶表面的第一区域和具有第二顶表面的第二区域，所述第二顶表面相对于所述第一顶表面低于所述第一顶表面 所述第一区域包括穿透其中的第一通孔，所述第二区域包括贯穿其中的第二通孔，填充所述第一通孔的第一导电图案，至少部分地填充所述第二通孔的第二导电图案， 可以提供第一导电图案上的隧道结图案和耦合到第二导电图案的接触插塞。 此外，还可以提供一种制造存储器件的方法。

公开(公告)号：US09502643B2

公开(公告)日：2016-11-22

申请号：US14606157

申请日：2015-01-27

Applicant: Byoungjae Bae ,  Jongchul Park ,  Shin Kwon ,  Inho Kim ,  Changwoo Sun

Inventor： Byoungjae Bae ,  Jongchul Park ,  Shin Kwon ,  Inho Kim ,  Changwoo Sun

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/08

Abstract: A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成导电柱，在导电柱之间依次形成牺牲层和模制结构，在模制结构上形成导电层，使得导电层连接到导电柱上， 去除牺牲层以形成气隙，去除模制结构以形成扩张空气间隙，并且图案化导电层以打开膨胀的气隙。

公开(公告)号：US20160149123A1

公开(公告)日：2016-05-26

申请号：US14919723

申请日：2015-10-21

Applicant: Jongchul PARK ,  Hyungjoon KWON

Inventor： Jongchul PARK ,  Hyungjoon KWON

IPC: H01L43/12 ,  H01L21/3065

CPC classification number: H01L43/12 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32623 ,  H01J2237/083 ,  H01J2237/3174 ,  H01J2237/334

Abstract: A pattern-forming method includes providing a first ion beam at a first incidence angle and a second ion beam at a second incidence angle to a surface of an etch target layer formed on a substrate. Patterns are formed by patterning the etch target layer using the first and second ion beams. The first ion beam and the second ion beam are substantially symmetrical to each other with respect to a normal line that is perpendicular to a top surface of the substrate. Each of the first and second incidence angles is greater than 0 degrees and smaller than an angle obtained by subtracting a predetermined angle from 90 degrees.

Abstract translation: 图案形成方法包括以第一入射角提供第一离子束，并以第二入射角提供第二离子束到形成在衬底上的蚀刻目标层的表面。 通过使用第一和第二离子束图案化蚀刻目标层来形成图案。 第一离子束和第二离子束相对于垂直于衬底顶表面的法线基本上彼此对称。 第一入射角和第二入射角中的每一个大于0度并且小于通过从90度减去预定角度而获得的角度。

公开(公告)号：US20160035969A1

公开(公告)日：2016-02-04

申请号：US14703842

申请日：2015-05-04

Applicant: Shin-Jae KANG ,  JONGCHUL PARK ,  BYOUNGJAE BAE ,  Jaesuk KWON ,  Hyunsoo SHIN

Inventor： Shin-Jae KANG ,  JONGCHUL PARK ,  BYOUNGJAE BAE ,  Jaesuk KWON ,  Hyunsoo SHIN

IPC: H01L43/02 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of fabricating a magnetic memory device is provided. The method may include sequentially forming a first magnetic layer, a tunnel barrier layer, and a second magnetic layer on a substrate, forming a mask pattern on the second magnetic layer to expose a portion of the second magnetic layer, forming a capping insulating layer on a sidewall of the mask pattern and the portion of the second magnetic layer, injecting an oxygen ion into the portion of the second magnetic layer through the capping insulating layer to form an oxide layer, anisotropically etching the capping insulating layer to form a capping spacer, and patterning the oxide layer, the tunnel barrier layer, and the first magnetic layer using the mask pattern and the capping spacer.

Abstract translation: 提供一种制造磁存储器件的方法。 该方法可以包括在衬底上顺序地形成第一磁性层，隧道势垒层和第二磁性层，在第二磁性层上形成掩模图案以暴露第二磁性层的一部分，形成封盖绝缘层 掩模图案的侧壁和第二磁性层的部分，通过封盖绝缘层将氧离子注入到第二磁性层的部分中以形成氧化物层，各向异性地蚀刻封盖绝缘层以形成封盖间隔物， 以及使用掩模图案和封盖间隔物图案化氧化物层，隧道势垒层和第一磁性层。

公开(公告)号：US20150311253A1

公开(公告)日：2015-10-29

申请号：US14602490

申请日：2015-01-22

Applicant: Young-Seok CHOI ,  Jaehun SEO ,  Hyun-woo YANG ,  Jongchul PARK

Inventor： Young-Seok CHOI ,  Jaehun SEO ,  Hyun-woo YANG ,  Jongchul PARK

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: Provided is a memory device, including a memory element on a substrate; a protection insulating pattern covering a side surface of the memory element and exposing a top surface of the memory element; an upper mold layer on the protection insulating pattern; and a bit line on and connected to the memory element, the bit line extending in a first direction, the protection insulating pattern including a first protection insulating pattern covering a lower side surface of the memory element; and a second protection insulating pattern covering an upper side surface of the memory element and including a different material from the first protection insulating pattern.

Abstract translation: 提供了一种存储器件，其包括在衬底上的存储元件; 覆盖存储元件的侧表面并暴露存储元件的顶表面的保护绝缘图案; 保护绝缘图案上的上模层; 以及位于所述存储元件上的位线，所述位线沿第一方向延伸，所述保护绝缘图案包括覆盖所述存储元件的下侧表面的第一保护绝缘图案; 以及覆盖存储元件的上侧表面并且包括与第一保护绝缘图案不同的材料的第二保护绝缘图案。

公开(公告)号：US20140349413A1

公开(公告)日：2014-11-27

申请号：US14225401

申请日：2014-03-25

Applicant: Sungyoon CHUNG ,  JINHYE BAE ,  HYUNGJOON KWON ,  JONGCHUL PARK ,  WONJUN LEE

Inventor： Sungyoon CHUNG ,  JINHYE BAE ,  HYUNGJOON KWON ,  JONGCHUL PARK ,  WONJUN LEE

IPC: H01L43/12 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A method of manufacturing a semiconductor device may include forming a material layer on a substrate, performing a selective oxidation process to form a capping oxide layer on a first surface of the material layer, wherein a second surface of the material layer is not oxidized, and etching the material layer through the second surface to form a material pattern. An etch rate of the capping oxide layer is less than an etch rate of the material layer. A semiconductor device may include a lower electrode on a substrate, a data storage part on a top surface of the lower electrode, an upper electrode on the data storage part, and a capping oxide layer arranged on at least a portion of a top surface of the upper electrode. The capping oxide layer may include an oxide formed by oxidation of an upper surface of the upper electrode.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成材料层，进行选择性氧化工艺以在材料层的第一表面上形成覆盖氧化物层，其中材料层的第二表面不被氧化，以及 通过第二表面蚀刻材料层以形成材料图案。 覆盖氧化物层的蚀刻速率小于材料层的蚀刻速率。 半导体器件可以包括在基板上的下电极，在下电极的顶表面上的数据存储部分，数据存储部分上的上电极，以及覆盖氧化物层，其设置在 上电极。 覆盖氧化物层可以包括通过氧化上部电极的上表面形成的氧化物。

公开(公告)号：US20140294345A1

公开(公告)日：2014-10-02

申请号：US14306217

申请日：2014-06-16

Applicant: Victor Il'ich Kopp ,  Jonathan Singer ,  Daniel Neugroschl ,  Jongchul Park ,  Mitchell S. Wlodawski

Inventor： Victor Il'ich Kopp ,  Jonathan Singer ,  Daniel Neugroschl ,  Jongchul Park ,  Mitchell S. Wlodawski

IPC: G02B6/28

CPC classification number: G02B6/30

Abstract: The inventive optical component assembly advantageously enables a multi-waveguide optical component (such as the inventive optical fiber coupler array, a multi-core optical fiber, etc.), to be coupled to at least one waveguide of an optical device at a predefined coupling angle. The optical component assembly of the present invention comprises a multi-waveguide optical component with an output end, a prism having an input surface, an output surface, and an internal reflective surface with a predefined reflection angle, and a GRIN lens, positioned between the component output end and the prism input surface, along a longitudinal axis of the multi-waveguide optical component. In accordance with the present invention, the length of the GRIN lens, and its refractive index gradient profile are optimized to form an optical image of the output end of the multi-waveguide optical component, at the output surface of the prism, thus enabling the output surface of the prism to be coupled to at least one waveguide of an optical device, with the predefined reflection angle corresponding to the angle at which the multi-waveguide optical component may be coupled to the optical device.

Abstract translation: 本发明的光学部件组件有利地使得多波导光学部件（例如本发明的光纤耦合器阵列，多芯光纤等）能够以预定的耦合耦合到光学器件的至少一个波导 角度。 本发明的光学部件组件包括具有输出端的多波导光学部件，具有输入表面的棱镜，输出表面和具有预定反射角的内部反射表面，以及位于 分量输出端和棱镜输入表面沿着多波导光学部件的纵向轴线。 根据本发明，GRIN透镜的长度及其折射率梯度分布被优化以在棱镜的输出表面上形成多波导光学部件的输出端的光学图像，因此能够 所述棱镜的输出表面将被耦合到光学装置的至少一个波导，其中所述预定反射角度对应于所述多波导光学部件可耦合到所述光学装置的角度。