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    Enhanced power managing unit (PMU) in a multiprocessor chip
    5.
    发明授权
    Enhanced power managing unit (PMU) in a multiprocessor chip 失效
    增强功率管理单元（PMU）在多处理器芯片中

    公开(公告)号：US5918061A

    公开(公告)日：1999-06-29

    申请号：US966631

    申请日：1997-11-10

    申请人： Bobby Babak Nikjou

    发明人： Bobby Babak Nikjou

    IPC分类号： G06F1/06 ,  G06F1/24 ,  G06F1/32 ,  G06F1/00

    CPC分类号： G06F1/3237 ,  G06F1/06 ,  G06F1/24 ,  G06F1/3203 ,  Y02B60/1221

    摘要： A power management circuit for use with multiple processors integrated on the same chip where one or more of the processors may run at different clock speeds from the others or be stopped. Clock generation circuitry including a power management unit which provides three power management modes, namely power down mode, idle mode and standby mode, plus separate control of each microprocessor core is utilized. In power down mode, the clocks that drive the general purpose processor core, and the other processors and all peripherals are stopped and the oscillator circuit which provides the clock signals to a circuit used to generate the clock phases used by the processors and peripherals are shut off. In idle mode, only the general purpose microprocessor clock is stopped while the peripherals are running. Standby mode is similar to power down mode in that the clocks that drive the general purpose microprocessor and the other processors and all peripheral clocks are stopped. However, unlike power down mode, during standby mode, the oscillator and the associated clock generation circuitry keep running so the part can wake up quickly. In providing for the separate control of the additional microprocessor cores, in addition to allowing the user to stop the additional cores when they are not needed, the additional cores are stopped when the part comes out of a reset thus preventing the additional cores from executing any program code until after the general purpose microprocessor core has completed its initialization and uploaded application program needed by other cores or processor.

    摘要翻译： 一种电源管理电路，用于集成在同一芯片上的多个处理器，其中一个或多个处理器可以以与其他处理器不同的时钟速度运行或停止。 包括提供三种功率管理模式的功率管理单元的时钟产生电路，即断电模式，空闲模式和待机模式，以及每个微处理器核心的单独控制。 在断电模式下，驱动通用处理器内核的时钟以及其他处理器和所有外设都停止工作，并且将用于产生处理器和外设使用的时钟相位的电路提供时钟信号的振荡器电路关闭 关闭 在空闲模式下，外设运行时只有通用微处理器时钟停止。 待机模式类似于掉电模式，因为驱动通用微处理器，其他处理器和所有外设时钟的时钟都被停止。 然而，与掉电模式不同，在待机模式下，振荡器和相关的时钟发生电路保持运行，因此器件可以快速唤醒。 在提供对附加微处理器核心的单独控制的同时，除了允许用户在不需要附加核心之外停止附加核心的情况下，当部件退出复位时，附加核心被停止，从而防止附加核心执行任何 程序代码，直到通用微处理器核心完成其初始化并上传其他核心或处理器所需的应用程序为止。