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    Peripheral protocol negotiation
    3.
    发明授权
    Peripheral protocol negotiation 有权
    外设协议协商

    公开(公告)号：US09547615B2

    公开(公告)日：2017-01-17

    申请号：US13977822

    申请日：2011-10-01

    申请人： Dennis M. Bell ,  Stephen S. Pawlowski

    发明人： Dennis M. Bell ,  Stephen S. Pawlowski

    IPC分类号： G06F13/00 ,  G06F13/38 ,  G06F13/14 ,  G06F9/44 ,  G06F13/42

    CPC分类号： G06F13/387 ,  G06F9/4413 ,  G06F13/14 ,  G06F13/38 ,  G06F13/4221

    摘要： Systems and methods of operating a computing system may involve utilizing at least one of a peripheral protocol negotiation and a universal connector to determine a peripheral device protocol, and reconfiguring a computer device to accommodate that peripheral device protocol. Upon such a reconfiguration, the peripheral protocol negotiation may “step aside”, and one or more subsequent communications between a host computer and the peripheral device utilizing the peripheral device protocol may start.

    摘要翻译： 操作计算系统的系统和方法可以包括利用外围协议协商和通用连接器中的至少一个来确定外围设备协议，以及重新配置计算机设备以适应该外围设备协议。 在这样的重新配置中，外围协议协商可以“搁置”，并且可以开始使用外围设备协议的主计算机和外围设备之间的一个或多个后续通信。

    Quad pumped bus architecture and protocol
    4.
    发明授权
    Quad pumped bus architecture and protocol 失效
    四泵浦总线架构和协议

    公开(公告)号：US06807592B2

    公开(公告)日：2004-10-19

    申请号：US09925691

    申请日：2001-08-10

    申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    IPC分类号： G06F1300

    CPC分类号： G06F13/4217

    摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

    摘要翻译： 双向多点处理器总线连接到多个总线代理。 可以通过以多抽头信令模式操作总线来增加总线吞吐量，其中多个信息元素以驱动代理以总线时钟频率的倍数的速率被驱动到总线上。 驱动代理还激活选通以识别信息元素的采样点。 可以例如使用双泵浦信号模式来驱动请求的信息元素，其中在一个总线时钟周期期间驱动两个信息元素。 数据线传输的数据元素例如可以使用四泵浦信号模式来驱动，其中四个数据元件在一个总线时钟周期内被驱动。 可以以偏移或交错布置临时地激活多个选通信号，以减少选通信号的频率。 可以通过仅使用选通信号的一种类型的边缘（例如，上升沿或下降沿）来提高采样对称性，以识别采样点。

    Response and data phases in a highly pipelined bus architecture
    5.
    发明授权
    Response and data phases in a highly pipelined bus architecture 失效
    高度流水线总线架构中的响应和数据阶段

    公开(公告)号：US06804735B2

    公开(公告)日：2004-10-12

    申请号：US09784244

    申请日：2001-02-14

    申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    IPC分类号： G06F1300

    CPC分类号： G06F13/4217

    摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.

    摘要翻译： 可用于增强的高流水线总线架构中的总线代理。 在一个实施例中，总线代理包括目标就绪接口，用于一组响应信号的一组响应接口和数据总线忙接口以及用于总线时钟信号的总线时钟接口。 该实施例的总线代理还包括总线控制器逻辑以跟踪包括事务N-1和事务N的多个事务，总线控制器能够为事务N断言目标就绪信号，如果总线代理正在断言数据 忙信号用于事务N-1，并取消对数据忙信号的否定。

    Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals
    6.
    发明授权
    Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals 有权
    将地址和数据线上的中断请求信号转换为中断消息信号的机制

    公开(公告)号：US06401153B2

    公开(公告)日：2002-06-04

    申请号：US09329001

    申请日：1999-06-08

    申请人： Stephen S. Pawlowski

    发明人： Stephen S. Pawlowski

    IPC分类号： G06F946

    CPC分类号： G06F13/24

    摘要： In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data signals. The apparatus also includes decode logic to receive at least some of the address signals and data signals and provide a decoded signal at one of several decode output lines of the decode logic. A redirection table includes a send pending bit that is set responsive to the decode signal. In another embodiment, an apparatus includes dedicated interrupt ports to receive an interrupt request signal. The apparatus also includes address and data ports capable of receiving an interrupt request signal in the form of address signals and data signals, and decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals. A redirection table includes a send pending bit to be set in response to either the interrupt request signal at the dedicated interrupt ports or in response to the decode signal.

    摘要翻译： 在本发明的一个实施例中，一种装置包括用于接收地址信号和数据信号形式的中断请求信号的地址和数据端口。 该装置还包括用于接收地址信号和数据信号中的至少一些的解码逻辑，并且在解码逻辑的多个解码输出行之一提供解码信号。 重定向表包括响应于解码信号设置的发送挂起位。 在另一个实施例中，装置包括用于接收中断请求信号的专用中断端口。 该装置还包括能够以地址信号和数据信号的形式接收中断请求信号的地址和数据端口，以及解码逻辑，以便响应于接收到中断请求信号的接收而在多条解码输出线之一提供解码信号 地址信号和数据信号的形式。 重定向表包括响应于专用中断端口处的中断请求信号或响应于解码信号而被设置的发送挂起位。

    Method and apparatus for tracking transactions in a pipelined bus
    7.
    发明授权
    Method and apparatus for tracking transactions in a pipelined bus 失效
    用于跟踪流水线总线中的交易的方法和装置

    公开(公告)号：US5696910A

    公开(公告)日：1997-12-09

    申请号：US533919

    申请日：1995-09-26

    申请人： Stephen S. Pawlowski

    发明人： Stephen S. Pawlowski

    IPC分类号： G06F13/42 ,  H01J13/00 ,  G06F13/38

    CPC分类号： G06F13/4217

    摘要： A method and apparatus for tracking transactions in a pipelined bus includes a bus state tracking queue and control logic. The bus state tracking queue maintains a record of bus transaction information for each of a plurality of transactions pending on the bus. The control logic, coupled to the bus state tracking queue, updates the status of the plurality of transactions in the bus state tracking queue as the transactions progress through the pipeline.

    摘要翻译： 用于跟踪流水线总线中的事务的方法和装置包括总线状态跟踪队列和控制逻辑。 总线状态跟踪队列为总线上待处理的多个事务中的每一个维护总线事务信息的记录。 当事务通过流水线进行时，耦合到总线状态跟踪队列的控制逻辑更新总线状态跟踪队列中的多个事务的状态。

    High bandwidth self-timed data clocking scheme for memory bus implementation
    8.
    发明授权
    High bandwidth self-timed data clocking scheme for memory bus implementation 失效
    用于存储器总线实现的高带宽自定时数据时钟方案

    公开(公告)号：US5550533A

    公开(公告)日：1996-08-27

    申请号：US339635

    申请日：1994-11-14

    申请人： Stephen S. Pawlowski

    发明人： Stephen S. Pawlowski

    IPC分类号： G06F13/42 ,  H04L1/16 ,  G06F1/12 ,  H04Q1/30

    CPC分类号： G06F13/4239

    摘要： A clocking scheme for transferring data between electronic devices. The clocking scheme includes sending a data request signal from a first device to a second device during a first system clocking period. The second device then sends the requested data and a corresponding data validation signal to the first device. The data validation signal latches the data into the second device. The data is latched by the validation signal in a time period that is typically shorter than the clocking period of the system clock.

    摘要翻译： 用于在电子设备之间传输数据的时钟方案。 时钟方案包括在第一系统时钟周期期间将数据请求信号从第一设备发送到第二设备。 然后，第二设备将所请求的数据和相应的数据验证信号发送到第一设备。 数据验证信号将数据锁存到第二个设备中。 在通常比系统时钟的时钟周期更短的时间段内，该数据被验证信号锁存。

    Snoop phase in a highly pipelined bus architecture
    10.
    发明授权
    Snoop phase in a highly pipelined bus architecture 有权
    Snoop阶段在高度流水线的总线架构中

    公开(公告)号：US06880031B2

    公开(公告)日：2005-04-12

    申请号：US09783784

    申请日：2001-02-14

    申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    IPC分类号： G06F13/36 ,  G06F13/42 ,  G06F13/14 ,  G06F12/00

    CPC分类号： G06F13/4217

    摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic capable of sensing or asserting one or more of a set of snoop status signals for transaction N on the snoop status interfaces during a snoop phase to start in a bus cycle upon the later of three or more bus clock cycles of the bus clock signal after a beginning of a bus cycle of an the assertion of an address strobe signal for transaction N or two or more bus clock cycles of the bus clock signal after a beginning of a bus cycle in which a most recent snoop phase begins.

    摘要翻译： 可用于增强的高流水线总线架构中的总线代理。 在一个实施例中，总线代理包括一组窥探状态接口，地址选通信号接口和用于总线时钟信号的总线时钟接口。 该实施例的总线代理还包括总线控制器逻辑，其能够在探测阶段期间在监听阶段中在三个或更多的后期的总线周期中检测或断言用于事件N的一组窥探状态信号中的一个或多个窥探状态信号 总线时钟信号的总线时钟周期在总线周期开始之后，在总线周期开始之后断言事务N的地址选通信号或总线时钟信号的两个或多个总线时钟周期，其中a 最近的窥探阶段开始了。