公开(公告)号：US11184005B2

公开(公告)日：2021-11-23

申请号：US17037522

申请日：2020-09-29

申请人： Ben Sheen

发明人： Ben Sheen

IPC分类号： H03K19/173 ,  H03K19/17736 ,  H03K19/1776

摘要： A field programmable device or software-defined hardware can change its functions by using software codes to alter the routing path of interconnect signal lines or the electrical properties of fundamental building elements. The field programmable device includes I/O interface blocks and signal processing blocks comprising analog signal processing units, digital signal processing units, memory units, clock units, and other supporting functional units which are electrically connected by user programmable interconnect signal lines. The analog signal processing functions can be altered by changing the electrical properties of fundamental building elements as well as the programmable signal lines after the device is manufactured.

公开(公告)号：US20210105015A1

公开(公告)日：2021-04-08

申请号：US17037522

申请日：2020-09-29

申请人： Ben Sheen

发明人： Ben Sheen

IPC分类号： H03K19/173 ,  H03K19/1776 ,  H03K19/17736

摘要： A field programmable device or software-defined hardware can change its functions by using software codes to alter the routing path of interconnect signal lines or the electrical properties of fundamental building elements. The field programmable device includes I/O interface blocks and signal processing blocks comprising analog signal processing units, digital signal processing units, memory units, clock units, and other supporting functional units which are electrically connected by user programmable interconnect signal lines. The analog signal processing functions can be altered by changing the electrical properties of fundamental building elements as well as the programmable signal lines after the device is manufactured.

公开(公告)号：US20100157687A1

公开(公告)日：2010-06-24

申请号：US12645337

申请日：2009-12-22

申请人： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

发明人： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

IPC分类号： G11C16/06 ,  G11C16/16

CPC分类号： G11C16/16

摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

摘要翻译： 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与之绝缘。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

公开(公告)号：US07215573B2

公开(公告)日：2007-05-08

申请号：US11212206

申请日：2005-08-25

申请人： Tseng-Yi Liu ,  Prateep Tuntasood ,  Ben Sheen

发明人： Tseng-Yi Liu ,  Prateep Tuntasood ,  Ben Sheen

IPC分类号： G11C11/34

CPC分类号： G11C16/3418

摘要： A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a plurality of column lines with each column line connected to a first terminal of a different column of cells. The array also has a plurality of first row lines, with each first row line connected to a second terminal of a different row of cells. The array also has a plurality of second row lines, with each second row line connected to a third terminal of a different row of cells. Finally, the array has a plurality of third row lines with each third row line connected to a fourth terminal of a different row of cells. A column decoder is connected to the plurality of column lines. A first row decoder is connected to the plurality of first row lines. A second row decoder is connected to the plurality of second row lines. A third row decoder is connected to the plurality of third row lines. During an operation of a selected cell, the column decoder selects one of the plurality of column lines, with the one column line selected connected to the first terminal of the selected cell. The first row decoder selects one of the plurality of first row lines with the one first row line selected connected to the second terminal of the selected cell. The second row decoder selects a first plurality of second row lines, with one of the first plurality of second row lines connected to the third terminal of the selected cell. The third row decoder selects a second plurality of third row lines, with one of the second plurality of third row lines connected to the fourth terminal of the selected cell. Finally, the first plurality of second row lines, other than the one second row line, are connected to cells arranged in rows other than rows of cells to which the second plurality of third row lines are connected. The interconnection minimizes programming disturbance.

摘要翻译： 存储器阵列具有以多个行和列布置的多个存储单元。 每个小区至少有四个终端。 阵列具有多条列线，每条列线连接到不同列的单元的第一端。 阵列还具有多个第一行线，其中每条第一行线连接到不同行单元的第二端。 阵列还具有多个第二行线，其中每条第二行线连接到不同行单元的第三端。 最后，该阵列具有多个第三行线，每条第三行线连接到不同行单元格的第四个终端。 列解码器连接到多条列线。 第一行解码器连接到多个第一行行。 第二行解码器连接到多条第二行线。 第三行解码器连接到多个第三行线。 在所选择的单元的操作期间，列解码器选择多条列线中的一条，其中选择一条列线连接到所选择的单元的第一端。 第一行解码器选择多个第一行中的一行，其中选择的一条第一行选择连接到所选择的单元的第二端。 第二行解码器选择第一多个第二行行，其中第一多个第二行行中的一个连接到所选择的单元格的第三个终端。 第三排解码器选择第二多个第三行线，其中第二多个第三行线中的一条连接到所选择的单元的第四端子。 最后，除了一条第二行线之外的第一多个第二行线连接到排列成与第二多个第三行线连接的单元行以外的行的单元。 互连最大限度地减少编程干扰。

公开(公告)号：US07239550B2

公开(公告)日：2007-07-03

申请号：US11255905

申请日：2005-10-20

申请人： Jonathan G. Pabustan ,  Ben Sheen

发明人： Jonathan G. Pabustan ,  Ben Sheen

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/3459

摘要： The present invention relates to a method of a programming a select non-volatile memory cell in a plurality of serially connected non-volatile memory cells with a serially connected select transistor. Each of the non-volatile memory cells has a control gate for receiving a programming voltage and the select transistor has a select gate for receiving a select voltage. The method comprises applying the programming voltage to the control gate of the select non-volatile memory cell in a program command sequence. The magnitude of the select voltage to the select gate of the select transistor within the program command sequence is then varied. The method can be applied to non-volatile cells in a NAND or NOR architecture.

摘要翻译： 本发明涉及一种使用串行连接的选择晶体管对多个串行连接的非易失性存储单元中的选择非易失性存储单元进行编程的方法。 每个非易失性存储单元具有用于接收编程电压的控制栅极，并且选择晶体管具有用于接收选择电压的选择栅极。 该方法包括以编程命令序列将编程电压施加到选择非易失性存储单元的控制栅极。 然后，改变在程序命令序列内选择晶体管的选择栅极的选择电压的大小。 该方法可以应用于NAND或NOR架构中的非易失性单元。

公开(公告)号：US20070047298A1

公开(公告)日：2007-03-01

申请号：US11212206

申请日：2005-08-25

申请人： Tseng-Yi Liu ,  Prateep Tuntasood ,  Ben Sheen

发明人： Tseng-Yi Liu ,  Prateep Tuntasood ,  Ben Sheen

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a plurality of column lines with each column line connected to a first terminal of a different column of cells. The array also has a plurality of first row lines, with each first row line connected to a second terminal of a different row of cells. The array also has a plurality of second row lines, with each second row line connected to a third terminal of a different row of cells. Finally, the array has a plurality of third row lines with each third row line connected to a fourth terminal of a different row of cells. A column decoder is connected to the plurality of column lines. A first row decoder is connected to the plurality of first row lines. A second row decoder is connected to the plurality of second row lines. A third row decoder is connected to the plurality of third row lines. During an operation of a selected cell, the column decoder selects one of the plurality of column lines, with the one column line selected connected to the first terminal of the selected cell. The first row decoder selects one of the plurality of first row lines with the one first row line selected connected to the second terminal of the selected cell. The second row decoder selects a first plurality of second row lines, with one of the first plurality of second row lines connected to the third terminal of the selected cell. The third row decoder selects a second plurality of third row lines, with one of the second plurality of third row lines connected to the fourth terminal of the selected cell. Finally, the first plurality of second row lines, other than the one second row line, are connected to cells arranged in rows other than rows of cells to which the second plurality of third row lines are connected. The interconnection minimizes programming disturbance.

公开(公告)号：US07974136B2

公开(公告)日：2011-07-05

申请号：US12645337

申请日：2009-12-22

申请人： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Der-Tsyr Fan ,  Yaw Wen Hu ,  Prateep Tuntasood

发明人： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Der-Tsyr Fan ,  Yaw Wen Hu ,  Prateep Tuntasood

IPC分类号： G11C16/04

CPC分类号： G11C16/16

摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

摘要翻译： 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

公开(公告)号：US07668013B2

公开(公告)日：2010-02-23

申请号：US12027654

申请日：2008-02-07

申请人： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

发明人： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

IPC分类号： G11C16/04

CPC分类号： G11C16/16

摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

摘要翻译： 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

公开(公告)号：US07434092B2

公开(公告)日：2008-10-07

申请号：US11063316

申请日：2005-02-22

申请人： Chih-Chieh Wang ,  Jonathan G. Pabustan ,  Ben Sheen

发明人： Chih-Chieh Wang ,  Jonathan G. Pabustan ,  Ben Sheen

IPC分类号： G06F11/00

CPC分类号： G11C29/846 ,  G06F11/1008 ,  G11C29/02 ,  G11C29/027 ,  G11C29/028 ,  G11C29/44 ,  G11C29/70 ,  G11C2029/0407 ,  G11C2029/4402 ,  G11C2229/723

摘要： Redundantly repaired semiconductor memory and method in which the configuration data for the memory is stored in an area of the main memory array which is known to be free of bad bits, along with a signature code which serves as a pointer and verifies the validity of the configuration data. In one disclosed embodiment, the data is stored in a configuration memory which is divided into a plurality of areas of equal size and known starting addresses. The number of areas is greater than the number of permitted repairs, and the areas which do not contain defects are available for storing configuration data including device settings, repair information, and the like.

摘要翻译： 冗余修复的半导体存储器和方法，其中用于存储器的配置数据被存储在已知没有坏位的主存储器阵列的区域中，以及用作指针的签名代码，并验证其的有效性 配置数据。 在一个公开的实施例中，数据被存储在配置存储器中，该配置存储器被分成多个相同大小的区域和已知的起始地址。 区域数量大于允许修理的数量，并且不存在缺陷的区域可用于存储包括设备设置，修理信息等的配置数据。

公开(公告)号：US20060190762A1

公开(公告)日：2006-08-24

申请号：US11063316

申请日：2005-02-22

申请人： Chih-Chieh Wang ,  Jonathan Pabustan ,  Ben Sheen

发明人： Chih-Chieh Wang ,  Jonathan Pabustan ,  Ben Sheen

IPC分类号： G06F11/00

CPC分类号： G11C29/846 ,  G06F11/1008 ,  G11C29/02 ,  G11C29/027 ,  G11C29/028 ,  G11C29/44 ,  G11C29/70 ,  G11C2029/0407 ,  G11C2029/4402 ,  G11C2229/723

摘要： Redundantly repaired semiconductor memory and method in which the configuration data for the memory is stored in an area of the main memory array which is known to be free of bad bits, along with a signature code which serves as a pointer and verifies the validity of the configuration data. In one disclosed embodiment, the data is stored in a configuration memory which is divided into a plurality of areas of equal size and known starting addresses. The number of areas is greater than the number of permitted repairs, and the areas which do not contain defects are available for storing configuration data including device settings, repair information, and the like.

摘要翻译： 冗余修复的半导体存储器和方法，其中用于存储器的配置数据被存储在已知没有坏位的主存储器阵列的区域中，以及用作指针的签名代码，并验证其的有效性 配置数据。 在一个所公开的实施例中，数据被存储在配置存储器中，该配置存储器被分成多个相同大小的区域和已知的起始地址。 区域数量大于允许修理的数量，并且不存在缺陷的区域可用于存储包括设备设置，修理信息等的配置数据。