公开(公告)号：US08385121B2

公开(公告)日：2013-02-26

申请号：US12948952

申请日：2010-11-18

Applicant: Vishal Sarin ,  Jung-Sheng Hoei ,  Jonathan Pabustan ,  Frankie F. Roohparvar

Inventor： Vishal Sarin ,  Jung-Sheng Hoei ,  Jonathan Pabustan ,  Frankie F. Roohparvar

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C7/16 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C27/005 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2216/14

Abstract: A memory has a memory array with a memory cell. The memory is adapted to program a first number of bits into the memory cell. The memory is adapted to sense a second number of bits, different from the first number of bits, from the memory cell.

Abstract translation: 存储器具有存储单元的存储器阵列。 存储器适于将第一数量的位编程到存储器单元中。 存储器适于从存储器单元感测与第一位数不同的第二数量的位。

公开(公告)号：US08169832B2

公开(公告)日：2012-05-01

申请号：US12909414

申请日：2010-10-21

Applicant: Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

Inventor： Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

IPC: G11C11/34

CPC classification number: G11C16/344 ,  G11C16/0483 ,  G11C16/3445

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

Abstract translation: 公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。 存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。 一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。 擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。 该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

公开(公告)号：US08023334B2

公开(公告)日：2011-09-20

申请号：US12262405

申请日：2008-10-31

Applicant: Jung-Sheng Hoei ,  Jonathan Pabustan ,  Vishal Sarin ,  William H. Radke ,  Frankie F. Roohparvar

Inventor： Jung-Sheng Hoei ,  Jonathan Pabustan ,  Vishal Sarin ,  William H. Radke ,  Frankie F. Roohparvar

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C5/063 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10

Abstract: A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed.

Abstract translation: 描述了补偿存储器单元信号线传播延迟的存储器件和编程和/或读取过程，例如增加总体阈值电压范围和可用的非易失性存储器单元状态。 可以通过表征存储单元信号线传播延迟来实现存储单元信号线传播延迟补偿，例如确定由于延迟引起的误差量，并且基于误差量预先补偿存储器单元的编程阈值电压 由所选存储单元信号线上的存储单元信号线传播延迟和单元位置引起。 或者，可以基于由存储器单元信号线传播延迟和单元引起的误差量感测所选择的存储器单元的阈值电压之后，对存储单元信号线传播延迟进行后补偿或预补偿微调 所选存储单元信号线上的位置。 还公开了其他方法，装置等。

公开(公告)号：US20100110798A1

公开(公告)日：2010-05-06

申请号：US12262405

申请日：2008-10-31

Applicant: Jung-Sheng Hoei ,  Jonathan Pabustan ,  Vishal Sarin ,  William H. Radke ,  Frankie F. Roohparvar

Inventor： Jung-Sheng Hoei ,  Jonathan Pabustan ,  Vishal Sarin ,  William H. Radke ,  Frankie F. Roohparvar

IPC: G11C16/10

CPC classification number: G11C16/26 ,  G11C5/063 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10

Abstract: A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed.

Abstract translation: 描述了补偿存储器单元信号线传播延迟的存储器件和编程和/或读取过程，例如增加总体阈值电压范围和可用的非易失性存储器单元状态。 可以通过表征存储单元信号线传播延迟来实现存储单元信号线传播延迟补偿，例如确定由于延迟引起的误差量，并且基于误差量预先补偿存储器单元的编程阈值电压 由所选存储单元信号线上的存储单元信号线传播延迟和单元位置引起。 或者，可以基于由存储器单元信号线传播延迟和单元引起的误差量感测所选择的存储器单元的阈值电压之后，对存储单元信号线传播延迟进行后补偿或预补偿微调 所选存储单元信号线上的位置。 还公开了其他方法，装置等。

公开(公告)号：US20120331217A1

公开(公告)日：2012-12-27

申请号：US13606471

申请日：2012-09-07

Applicant: Vishal Sarin ,  Frankie F. Roohparvar ,  Jonathan Pabustan ,  Jung-Sheng Hoei

Inventor： Vishal Sarin ,  Frankie F. Roohparvar ,  Jonathan Pabustan ,  Jung-Sheng Hoei

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7211

Abstract: In one or more embodiments, a memory device has an adjustable programming window with a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.

Abstract translation: 在一个或多个实施例中，存储器设备具有具有多个可编程电平的可调编程窗口。 移动编程窗口以补偿由于存储器件经历改变程序窗口的擦除/编程周期等因素而可实现的可靠程序和擦除阈值的变化。 在初始擦除/编程周期之前确定初始编程窗口。 然后随着编程窗口的改变，编程级别被移动，使得多个可编程级别仍然保留在程序窗口内并且随着程序窗口的改变而跟踪。

公开(公告)号：US20120117313A1

公开(公告)日：2012-05-10

申请号：US13351525

申请日：2012-01-17

Applicant: Vishal SARIN ,  Frankie F. Roohparvar ,  Jonathan Pabustan ,  Jung-Sheng Hoei

Inventor： Vishal SARIN ,  Frankie F. Roohparvar ,  Jonathan Pabustan ,  Jung-Sheng Hoei

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7211

Abstract: In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.

Abstract translation: 在一个或多个实施例中，公开了存储器件具有可编程窗口，其具有多个可编程级。 移动编程窗口以补偿由于存储器件经历改变程序窗口的擦除/编程周期等因素而可实现的可靠程序和擦除阈值的变化。 在初始擦除/编程周期之前确定初始编程窗口。 然后随着编程窗口的改变，编程级别被移动，使得多个可编程级别仍然保留在程序窗口内并且随着程序窗口的改变而跟踪。

公开(公告)号：US07864589B2

公开(公告)日：2011-01-04

申请号：US12191523

申请日：2008-08-14

Applicant: Vishal Sarin ,  Jonathan Pabustan ,  Frankie F. Roohparvar

Inventor： Vishal Sarin ,  Jonathan Pabustan ,  Frankie F. Roohparvar

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5644

Abstract: Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by a particular verify voltage of the ramp voltage signal in response to a digital count of the digital count signal. The memory cell turning on generates a bit line indication that causes the digital count to be compared to a representation of the target data to be programmed in the memory cell. The comparator circuit generates an indication when the digital count is greater than or equal to the target data.

Abstract translation: 提供了用于缓解存储器件中的失控编程的方法，用于程序验证存储器件的方法，存储器件和存储器系统。 在一种这样的方法中，通过数字计数信号产生斜坡电压信号。 程序验证的存储单元响应于数字计数信号的数字计数，由斜坡电压信号的特定验证电压导通。 存储器单元导通产生位线指示，其使数字计数与要在存储器单元中编程的目标数据的表示进行比较。 当数字计数大于或等于目标数据时，比较器电路产生指示。

公开(公告)号：US07835190B2

公开(公告)日：2010-11-16

申请号：US12190409

申请日：2008-08-12

Applicant: Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

Inventor： Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

IPC: G11C11/34

CPC classification number: G11C16/344 ,  G11C16/0483 ,  G11C16/3445

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

Abstract translation: 公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。 存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。 一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。 擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。 该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

公开(公告)号：US20100039863A1

公开(公告)日：2010-02-18

申请号：US12191523

申请日：2008-08-14

Applicant: Vishal Sarin ,  Jonathan Pabustan ,  Frankie F. Roohparvar

Inventor： Vishal Sarin ,  Jonathan Pabustan ,  Frankie F. Roohparvar

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5644

Abstract: Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by a particular verify voltage of the ramp voltage signal in response to a digital count of the digital count signal. The memory cell turning on generates a bit line indication that causes the digital count to be compared to a representation of the target data to be programmed in the memory cell. The comparator circuit generates an indication when the digital count is greater than or equal to the target data.

Abstract translation: 提供了用于缓解存储器件中的失控编程的方法，用于程序验证存储器件的方法，存储器件和存储器系统。 在一种这样的方法中，通过数字计数信号产生斜坡电压信号。 程序验证的存储单元响应于数字计数信号的数字计数，由斜坡电压信号的特定验证电压导通。 存储器单元导通产生位线指示，其使数字计数与要在存储器单元中编程的目标数据的表示进行比较。 当数字计数大于或等于目标数据时，比较器电路产生指示。

公开(公告)号：US20090201744A1

公开(公告)日：2009-08-13

申请号：US12027654

申请日：2008-02-07

Applicant: Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

Inventor： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

Abstract translation: 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。