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    Method for forming different patterns using one mask
    1.
    发明授权
    Method for forming different patterns using one mask 有权
    使用一个掩模形成不同图案的方法

    公开(公告)号：US06296987B1

    公开(公告)日：2001-10-02

    申请号：US09421309

    申请日：1999-10-20

    Applicant: Benjamin Szu-Min Lin ,  Chien-Li Kuo

    Inventor： Benjamin Szu-Min Lin ,  Chien-Li Kuo

    IPC: G03F900

    CPC classification number: G03F7/70466 ,  G03F1/30 ,  G03F7/0035

    Abstract: A method for forming different patterns using one phase shifting mask. The phase shifting mask has a bit line contact pattern and a node contact pattern thereon. The exposure pattern is changed by using different defocus conditions. In a first defocus situation, the bit line contact pattern and the node contact pattern of the PSM are simultaneously transferred to a photoresist layer. However, in a second defocus situation, only the bit line contact pattern is transferred to the photoresist layer. A phase shifting mask thus can be used in two different photolithography processes.

    Abstract translation: 一种使用一个相移掩模形成不同图案的方法。 相移掩模具有位线接触图案和其上的节点接触图案。 通过使用不同的散焦条件改变曝光图案。 在第一散焦情况下，PSM的位线接触图案和节点接触图案被同时传送到光致抗蚀剂层。 然而，在第二散焦情况下，仅将位线接触图案转移到光致抗蚀剂层。 因此，相移掩模可用于两种不同的光刻工艺。

    Method for fabricating through-silicon via structure
    2.
    发明授权
    Method for fabricating through-silicon via structure 有权
    通硅结构制造方法

    公开(公告)号：US08202766B2

    公开(公告)日：2012-06-19

    申请号：US12487665

    申请日：2009-06-19

    Applicant: Chien-Li Kuo

    Inventor： Chien-Li Kuo

    IPC: H01L21/768 ,  H01L21/56

    CPC classification number: H01L21/76898

    Abstract: A method for fabricating through-silicon via structure includes the steps of: providing a semiconductor substrate; forming at least one semiconductor device on surface of the semiconductor substrate; forming a dielectric layer on the semiconductor device, in which the dielectric layer includes at least one via hole; forming a first conductive layer on the dielectric layer and filling the via hole; performing an etching process to form a through-silicon via in the first conductive layer, the dielectric layer, and the semiconductor substrate; depositing a second conductive layer in the through-silicon via and partially on the first conductive layer; and planarizing a portion of the second conductive layer until reaching the surface of the first conductive layer.

    Abstract translation: 一种用于制造穿硅通孔结构的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底的表面上形成至少一个半导体器件; 在所述半导体器件上形成电介质层，其中所述电介质层包括至少一个通孔; 在所述电介质层上形成第一导电层并填充所述通孔; 在所述第一导电层，所述电介质层和所述半导体衬底中进行蚀刻工艺以形成贯通硅通孔; 在所述穿硅通孔中并部分地在所述第一导电层上沉积第二导电层; 以及平坦化所述第二导电层的一部分直到到达所述第一导电层的表面。

    Electrical fuse structure
    6.
    发明授权
    Electrical fuse structure 有权
    电熔丝结构

    公开(公告)号：US08026573B2

    公开(公告)日：2011-09-27

    申请号：US12335510

    申请日：2008-12-15

    Applicant: Chien-Li Kuo ,  Yung-Chang Lin ,  Kuei-Sheng Wu ,  San-Fu Lin

    Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Kuei-Sheng Wu ,  San-Fu Lin

    IPC: H01L23/52

    CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element.

    Abstract translation: 公开了电熔丝结构。 电熔丝结构包括设置在半导体衬底的表面上的熔丝元件，与熔丝元件的一端电连接的阴极以及与熔丝元件的另一端电连接的阳极。 具体而言，压电应力层设置在熔丝元件的至少一部分上。

    Method for fabricating embedded static random access memory
    8.
    发明授权
    Method for fabricating embedded static random access memory 有权
    嵌入式静态随机存取存储器的制作方法

    公开(公告)号：US07588991B2

    公开(公告)日：2009-09-15

    申请号：US11779880

    申请日：2007-07-18

    Applicant: Tung-Hsing Lee ,  Chien-Li Kuo ,  Yun-San Huang ,  Chih-Ming Su ,  Buo-Chin Hsu

    Inventor： Tung-Hsing Lee ,  Chien-Li Kuo ,  Yun-San Huang ,  Chih-Ming Su ,  Buo-Chin Hsu

    IPC: H01L21/331

    CPC classification number: H01L27/1104 ,  H01L27/105 ,  H01L27/1116

    Abstract: The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.

    Abstract translation: 本发明提供了一种制造嵌入式静态随机存取存储器的方法，包括提供半导体衬底; 在所述半导体衬底上限定逻辑区域和存储单元区域，并分别在所述逻辑区域和所述存储器单元区域中至少限定第一导电器件区域和至少第二导电器件区域; 在所述存储单元区域和所述逻辑区域中的所述第二导电器件区域上形成图案化掩模，并且暴露所述逻辑区域中的所述第一导电器件区域; 在所述逻辑区域中暴露的第一导电器件区域上执行第一导电离子注入工艺; 并去除图案化掩模。

    MASK PATTERN AND METHOD FOR FORMING THE SAME
    9.
    发明申请
    MASK PATTERN AND METHOD FOR FORMING THE SAME 有权
    掩模图案及其形成方法

    公开(公告)号：US20080220341A1

    公开(公告)日：2008-09-11

    申请号：US11683778

    申请日：2007-03-08

    Applicant: Chuan-Hsien Fu ,  Chuen-Huei Yang ,  Chien-Li Kuo ,  Shu-Ru Wang ,  Yu-Lin Wang

    Inventor： Chuan-Hsien Fu ,  Chuen-Huei Yang ,  Chien-Li Kuo ,  Shu-Ru Wang ,  Yu-Lin Wang

    IPC: G03F1/00

    CPC classification number: G03F1/36

    Abstract: The invention provides a mask pattern. The mask pattern comprises at least a continuous pattern. Each of the continuous patterns has a first pattern, a second pattern and a set of assistance patterns. The assistant patterns are located between the first pattern to the second pattern. The first pattern, the assistant patterns and the second pattern together form a closed opening.

    Abstract translation: 本发明提供一种掩模图案。 掩模图案至少包括连续图案。 每个连续图案具有第一图案，第二图案和一组辅助图案。 辅助图案位于第一图案与第二图案之间。 第一种图案，辅助图案和第二图案一起形成封闭的开口。

    On-chip test circuit for assessing chip integrity
    10.
    发明授权
    On-chip test circuit for assessing chip integrity 有权
    用于评估芯片完整性的片上测试电路

    公开(公告)号：US07256475B2

    公开(公告)日：2007-08-14

    申请号：US11161304

    申请日：2005-07-29

    Applicant: Jui-Meng Jao ,  Chien-Li Kuo

    Inventor： Jui-Meng Jao ,  Chien-Li Kuo

    IPC: H01L23/00

    CPC classification number: G01R31/2884 ,  G01R31/2853 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/05001 ,  H01L2224/05085 ,  H01L2224/05568 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05599

    Abstract: A semiconductor chip includes an active inner circuit; a die seal ring surrounding the active inner circuit; a first circuit structure fabricated at a first corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the first circuit structure has a first solder pad; and a second circuit structure fabricated at a second corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the second circuit structure has a second solder pad.

    Abstract translation: 半导体芯片包括有源内部电路; 围绕有源内部电路的模具密封环; 第一电路结构，其制造在所述半导体芯片的位于所述模具密封环外部的第一角部并电连接到所述模具密封件，其中所述第一电路结构具有第一焊盘; 以及第二电路结构，其在所述半导体芯片的位于所述模具密封环的外部的第二角处制造并电连接到所述模具密封件，其中所述第二电路结构具有第二焊盘。

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