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    MIM TRANSISTOR
    2.
    发明申请
    MIM TRANSISTOR 有权
    MIM晶体管

    公开(公告)号：US20110095375A1

    公开(公告)日：2011-04-28

    申请号：US12984465

    申请日：2011-01-04

    Applicant: Benoit Froment ,  Etienne Robilliart

    Inventor： Benoit Froment ,  Etienne Robilliart

    IPC: H01L27/088

    CPC classification number: H01L49/003

    Abstract: The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.

    Abstract translation: 本发明涉及一种厚度在1至5个原子之间的导电层，绝缘栅极形成在导电层的一部分上。

    Forming of silicide areas in a semiconductor device
    4.
    发明申请
    Forming of silicide areas in a semiconductor device 有权
    在半导体器件中形成硅化物区域

    公开(公告)号：US20070099408A1

    公开(公告)日：2007-05-03

    申请号：US11592398

    申请日：2006-11-02

    Applicant: Delphine Aime ,  Benoit Froment

    Inventor： Delphine Aime ,  Benoit Froment

    IPC: H01L21/4763 ,  H01L21/3205

    CPC classification number: H01L29/66507 ,  H01L21/26513 ,  H01L21/28097

    Abstract: An embodiment of a method for forming silicide areas of different thicknesses in a device comprising first and second silicon areas, comprising the steps of: implanting antimony or aluminum in the upper portion of the first silicon areas; covering the silicon areas with a metallic material; and heating the device to transform all or part of the silicon areas into silicide areas, whereby the silicide areas formed at the level of the first silicon areas are thinner than the silicide areas formed at the level of the second silicon areas.

    Abstract translation: 一种用于在包括第一和第二硅区域的器件中形成不同厚度的硅化物区域的方法的实施例，包括以下步骤：在第一硅区域的上部注入锑或铝; 用金属材料覆盖硅区域; 并且加热该器件以将全部或部分硅区域转化为硅化物区域，由此形成在第一硅区域的层面处的硅化物区域比形成在第二硅片区域的硅化物区域薄。

    Method of manufacturing a vertical metal connection in an integrated circuit
    5.
    发明授权
    Method of manufacturing a vertical metal connection in an integrated circuit 有权
    在集成电路中制造垂直金属连接的方法

    公开(公告)号：US06627093B1

    公开(公告)日：2003-09-30

    申请号：US09673203

    申请日：2000-10-12

    Applicant: Benoit Froment ,  Phillipe Gayet ,  Erik Van Der Vegt

    Inventor： Benoit Froment ,  Phillipe Gayet ,  Erik Van Der Vegt

    IPC: H01L2100

    CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: At least one layer of a dielectric material 3 is deposited on a copper track 1 covered with an encapsulation layer 2. A cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer is deposited in said cavity to preclude diffusion of copper 7. The protective layer 7 at the bottom of the cavity 6 is subjected to an anisotropic etching treatment and also the encapsulation layer 2 is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching the encapsulation layer do not contaminate the dielectric material 3.

    Abstract translation: 至少一层电介质材料3沉积在被封装层2覆盖的铜轨道1上。在未来垂直连接位置的电介质材料层中蚀刻腔体6。 在所述空腔中沉积至少一个保护层以阻止铜7的扩散。对空腔6底部的保护层7进行各向异性蚀刻处理，并且还对封装层2进行蚀刻，之后空腔为 充满铜。 在蚀刻封装层期间粉碎的铜颗粒不会污染电介质材料3。

    MIM transistor
    6.
    发明授权
    MIM transistor 有权
    MIM晶体管

    公开(公告)号：US08354725B2

    公开(公告)日：2013-01-15

    申请号：US12984465

    申请日：2011-01-04

    Applicant: Benoit Froment ,  Etienne Robilliart

    Inventor： Benoit Froment ,  Etienne Robilliart

    IPC: H01L21/70 ,  H01L27/118

    CPC classification number: H01L49/003

    Abstract: The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.

    Abstract translation: 本发明涉及一种厚度在1至5个原子之间的导电层，绝缘栅极形成在导电层的一部分上。

    Gate electrode silicidation process
    7.
    发明授权
    Gate electrode silicidation process 有权
    栅电极硅化工艺

    公开(公告)号：US07622387B2

    公开(公告)日：2009-11-24

    申请号：US12065256

    申请日：2005-08-29

    Applicant: Vidya Kaushik ,  Benoit Froment

    Inventor： Vidya Kaushik ,  Benoit Froment

    IPC: H01L21/44

    CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/665

    Abstract: A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon with the metal layer therebetween. One of the silicon layers may be amorphous silicon whereas the other silicon layer may be polycrystalline silicon. The silicon between the metal layer and the gate dielectric may be deposited in two layers having different crystallinities. This process enables greater control to be exercised over the phase of the silicide resulting from this silicidation process.

    Abstract translation: 通过在其间沉积至少两层硅的金属层，由硅和金属形成完全硅化的栅电极。 硅层之一可以是非晶硅，而另一个硅层可以是多晶硅。 金属层和栅极电介质之间的硅可以沉积成具有不同结晶度的两层。 该过程使得能够在由该硅化过程产生的硅化物的相位上进行更大的控制。

    Gate Electrode Silicidation Process
    8.
    发明申请
    Gate Electrode Silicidation Process 有权
    栅电极硅化工艺

    公开(公告)号：US20080197498A1

    公开(公告)日：2008-08-21

    申请号：US12065256

    申请日：2005-08-29

    Applicant: Vidya Kaushik ,  Benoit Froment

    Inventor： Vidya Kaushik ,  Benoit Froment

    IPC: H01L29/49 ,  H01L21/283

    CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/665

    Abstract: A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon with the metal layer therebetween. One of the silicon layers may be amorphous silicon whereas the other silicon layer may be polycrystalline silicon. The silicon between the metal layer and the gate dielectric may be deposited in two layers having different crystallinities. This process enables greater control to be exercised over the phase of the silicide resulting from this silicidation process.

    Abstract translation: 通过在其间沉积至少两层硅的金属层，由硅和金属形成完全硅化的栅电极。 硅层之一可以是非晶硅，而另一个硅层可以是多晶硅。 金属层和栅极电介质之间的硅可以沉积成具有不同结晶度的两层。 该过程使得能够在由该硅化过程产生的硅化物的相位上进行更大的控制。

    Increasing the capacitance of a capacitive device by micromasking
    9.
    发明授权
    Increasing the capacitance of a capacitive device by micromasking 有权
    通过微掩模增加电容器件的电容

    公开(公告)号：US08295028B2

    公开(公告)日：2012-10-23

    申请号：US12074267

    申请日：2008-02-29

    Applicant: Benoit Froment

    Inventor： Benoit Froment

    IPC: H01G4/30

    CPC classification number: H01L21/32139 ,  H01L28/84

    Abstract: Capacitive coupling devices and methods of fabricating a capacitive coupling device are disclosed. The coupling device could include a stack of layers forming electrodes and at least one insulator. The insulator could include a region of doped silicon. The silicon could be doped with a species selected from Ce, Cr, Co, Cu, Dy, Er, Eu, Ho, Ir, Li, Lu, Mn, Pr, Rb, Sm, Sr, Tb, Tm, Yb, Y, Ac, Am, Ba, Be, Cd, Gd, Fe, La, Pb, Ni, Ra, Sc, Th, Hf, Tl, Sn, Np, Rh, U, Zn, Ag, and Yb in relief and forming roughnesses relative to the neighboring regions of the same level in the stack. The electrodes and the insulator form conformal layers above the doped silicon region.

    Abstract translation: 公开了电容耦合器件和制造电容耦合器件的方法。 耦合装置可以包括形成电极和至少一个绝缘体的一叠层。 绝缘体可以包括掺杂硅的区域。 该硅可掺杂选自Ce，Cr，Co，Cu，Dy，Er，Eu，Ho，Ir，Li，Lu，Mn，Pr，Rb，Sm，Sr，Tb，Tm，Yb，Y， Ac，Am，Ba，Be，Cd，Gd，Fe，La，Pb，Ni，Ra，Sc，Th，Hf，Tl，Sn，Np，Rh，U，Zn，Ag和Yb相对于浮雕和成型粗糙度 到堆叠中相同级别的相邻区域。 电极和绝缘体在掺杂硅区域之上形成共形层。

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