公开(公告)号：US20150117095A1

公开(公告)日：2015-04-30

申请号：US14129506

申请日：2013-10-31

Applicant: Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

Inventor： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

Abstract translation: 描述了一种用于提高读写余量的装置。 该装置包括：源线; 第一个位线 一列电阻存储器单元，该列的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到第一位线; 以及与所述第一位线并联的第二位线，所述第二位线用于解耦所述电阻存储器单元的位线上的读取和写入操作。 还描述了一种装置，其包括：源线; 有位 一列电阻存储器单元，列中的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到位线; 以及耦合到位线和源极线的源极线写入驱动器，其中源极线写入驱动器沿着电阻存储器单元的列分布。

公开(公告)号：US09478273B2

公开(公告)日：2016-10-25

申请号：US14129506

申请日：2013-10-31

Applicant: Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

Inventor： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

Abstract translation: 描述了一种用于提高读写余量的装置。 该装置包括：源线; 第一个位线 一列电阻存储器单元，该列的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到第一位线; 以及与所述第一位线并联的第二位线，所述第二位线用于解耦所述电阻存储器单元的位线上的读取和写入操作。 还描述了一种装置，其包括：源线; 有位 一列电阻存储器单元，列中的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到位线; 以及耦合到位线和源极线的源极线写入驱动器，其中源极线写入驱动器沿着电阻存储器单元的列分布。