公开(公告)号：US07657713B2

公开(公告)日：2010-02-02

申请号：US10948674

申请日：2004-09-24

申请人： Bok-Gue Park ,  Dong-Il Seo ,  Hyun-Soon Jang ,  Woo-Seop Jeong

发明人： Bok-Gue Park ,  Dong-Il Seo ,  Hyun-Soon Jang ,  Woo-Seop Jeong

IPC分类号： G06F13/14

CPC分类号： H04L12/56

摘要： A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.

摘要翻译： 包括多个分组引脚，同步存储器和分组控制器的存储器。 同步存储器与时钟信号同步地接收地址和控制信号。 当分组使能信号被激活时，分组控制器与时钟信号同步地通过分组引脚顺序地接收分组数据比特，并将输入的分组数据转换成地址和控制信号。 具体地，首先通过分组引脚输入的分组数据位表示操作模式。

公开(公告)号：US20050122819A1

公开(公告)日：2005-06-09

申请号：US11001974

申请日：2004-12-02

申请人： Bok-Gue Park ,  Woo-Seop Jeong

发明人： Bok-Gue Park ,  Woo-Seop Jeong

IPC分类号： G11C5/14 ,  G11C11/24 ,  G11C11/406 ,  G11C11/4074

CPC分类号： G11C11/40615 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4067

摘要： A power supply device in a semiconductor memory includes a power control means and a power generation means. The power control means divides a self-refresh section into an active-precharge mode and an idle mode depending on an operation characteristic of the semiconductor memory, and generates a control signal for controlling power strength applied to the semiconductor memory during operation in each mode. The power generation mode generates a different power level in response to a power control signal from the power control means to provide to the semiconductor memory. Meanwhile, the power supply device according to the present invention provides relatively strong power to the semiconductor memory a predetermined time period in advance of the active-precharge mode.

摘要翻译： 半导体存储器中的电源装置包括功率控制装置和发电装置。 功率控制装置根据半导体存储器的操作特性将自刷新部分划分为有效预充电模式和空闲模式，并且在每个模式下产生用于控制施加到半导体存储器的功率强度的控制信号。 发电模式响应于来自功率控制装置的功率控制信号而产生不同的功率电平以提供给半导体存储器。 同时，根据本发明的电源装置在有源预充电模式之前的预定时间段内向半导体存储器提供相对强大的功率。

公开(公告)号：US20050094631A1

公开(公告)日：2005-05-05

申请号：US10948674

申请日：2004-09-24

申请人： Bok-Gue Park ,  Dong-Il Seo ,  Hyun-Soon Jang ,  Woo-Seop Jeong

发明人： Bok-Gue Park ,  Dong-Il Seo ,  Hyun-Soon Jang ,  Woo-Seop Jeong

IPC分类号： G11C11/409 ,  H04L12/56 ,  H04L12/66

CPC分类号： H04L12/56

摘要： A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.

摘要翻译： 包括多个分组引脚，同步存储器和分组控制器的存储器。 同步存储器与时钟信号同步地接收地址和控制信号。 当分组使能信号被激活时，分组控制器与时钟信号同步地通过分组引脚顺序地接收分组数据比特，并将输入的分组数据转换成地址和控制信号。 具体地，首先通过分组引脚输入的分组数据位表示操作模式。

公开(公告)号：US20080195919A1

公开(公告)日：2008-08-14

申请号：US11865856

申请日：2007-10-02

申请人： Bok-gue Park ,  Uk-song Kang ,  Sang-jae Rhee

发明人： Bok-gue Park ,  Uk-song Kang ,  Sang-jae Rhee

IPC分类号： H03M13/03

CPC分类号： H03M13/19 ,  G06F11/1044 ,  H03M13/611

摘要： A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

摘要翻译： 半导体存储器件包括存储单元阵列和纠错码（ECC）引擎。 存储单元阵列在其中存储正常数据和奇偶校验数据的位。 ECC引擎在掩蔽模式中执行掩蔽操作，ECC引擎使用正常数据来计算奇偶校验数据。 正常数据包括要被更新的第一部分和将被掩蔽操作保存的第二部分。

公开(公告)号：US07260013B2

公开(公告)日：2007-08-21

申请号：US11001974

申请日：2004-12-02

申请人： Bok-Gue Park ,  Woo-Seop Jeong

发明人： Bok-Gue Park ,  Woo-Seop Jeong

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C8/00 ,  G05F1/10

CPC分类号： G11C11/40615 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4067

摘要： A power supply device in a semiconductor memory includes a power control means and a power generation means. The power control means divides a self-refresh section into an active-precharge mode and an idle mode depending on an operation characteristic of the semiconductor memory, and generates a control signal for controlling power strength applied to the semiconductor memory during operation in each mode. The power generation mode generates a different power level in response to a power control signal from the power control means to provide to the semiconductor memory. Meanwhile, the power supply device according to the present invention provides relatively strong power to the semiconductor memory a predetermined time period in advance of the active-precharge mode.

摘要翻译： 半导体存储器中的电源装置包括功率控制装置和发电装置。 功率控制装置根据半导体存储器的操作特性将自刷新部分划分为有效预充电模式和空闲模式，并且在每个模式下产生用于控制施加到半导体存储器的功率强度的控制信号。 发电模式响应于来自功率控制装置的功率控制信号而产生不同的功率电平以提供给半导体存储器。 同时，根据本发明的电源装置在有源预充电模式之前的预定时间段内向半导体存储器提供相对强大的功率。

公开(公告)号：US20080294934A1

公开(公告)日：2008-11-27

申请号：US12071024

申请日：2008-02-14

申请人： Bok-Gue Park

发明人： Bok-Gue Park

IPC分类号： G06F11/10

CPC分类号： G11C11/406 ,  G06F11/1012 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2029/0411 ,  G11C2211/4062

摘要： A semiconductor memory device may include a parity generating circuit, a memory cell array, an error calculating circuit and an error corrector. The parity generating circuit generates parities having different number of bits according to types of a partial array self-refresh mode, and selects one of the parities to output a first parity. The error calculating circuit calculates an error based on a first data corresponding to the input data and a second parity corresponding to the first parity and outputs a first error data. The error corrector corrects the first data based on the first data and the first error data.

摘要翻译： 半导体存储器件可以包括奇偶生成电路，存储单元阵列，误差计算电路和误差校正器。 奇偶产生电路根据部分阵列自刷新模式的类型产生具有不同数量的比特的奇偶校验，并且选择奇偶校验之一以输出第一奇偶校验。 误差计算电路基于对应于输入数据的第一数据和对应于第一奇偶校验的第二奇偶校验来计算误差，并输出第一误差数据。 错误校正器基于第一数据和第一错误数据来校正第一数据。

公开(公告)号：US08225171B2

公开(公告)日：2012-07-17

申请号：US12071024

申请日：2008-02-14

申请人： Bok-Gue Park

发明人： Bok-Gue Park

IPC分类号： G06F11/00

CPC分类号： G11C11/406 ,  G06F11/1012 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2029/0411 ,  G11C2211/4062

摘要： A semiconductor memory device may include a parity generating circuit, a memory cell array, an error calculating circuit and an error corrector. The parity generating circuit generates parities having different number of bits according to types of a partial array self-refresh mode, and selects one of the parities to output a first parity. The error calculating circuit calculates an error based on a first data corresponding to the input data and a second parity corresponding to the first parity and outputs a first error data. The error corrector corrects the first data based on the first data and the first error data.

摘要翻译： 半导体存储器件可以包括奇偶生成电路，存储单元阵列，误差计算电路和误差校正器。 奇偶产生电路根据部分阵列自刷新模式的类型产生具有不同数量的比特的奇偶校验，并且选择奇偶校验之一以输出第一奇偶校验。 误差计算电路基于对应于输入数据的第一数据和对应于第一奇偶校验的第二奇偶校验来计算误差，并输出第一误差数据。 错误校正器基于第一数据和第一错误数据来校正第一数据。

公开(公告)号：US08132086B2

公开(公告)日：2012-03-06

申请号：US11865856

申请日：2007-10-02

申请人： Bok-gue Park ,  Uk-song Kang ,  Sang-jae Rhee

发明人： Bok-gue Park ,  Uk-song Kang ,  Sang-jae Rhee

IPC分类号： G06F11/00

CPC分类号： H03M13/19 ,  G06F11/1044 ,  H03M13/611

摘要： A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

摘要翻译： 半导体存储器件包括存储单元阵列和纠错码（ECC）引擎。 存储单元阵列在其中存储正常数据和奇偶校验数据的位。 ECC引擎在掩蔽模式中执行掩蔽操作，ECC引擎使用正常数据来计算奇偶校验数据。 正常数据包括要被更新的第一部分和将被掩蔽操作保存的第二部分。

公开(公告)号：US20090059682A1

公开(公告)日：2009-03-05

申请号：US12202902

申请日：2008-09-02

申请人： Bok-Gue Park ,  Sang-Jae Rhee ,  Jae-Youn Youn

发明人： Bok-Gue Park ,  Sang-Jae Rhee ,  Jae-Youn Youn

IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C8/00

CPC分类号： G11C29/02 ,  G11C29/027 ,  G11C29/787

摘要： A semiconductor memory device includes a fuse box including a plurality of address antifuse circuits, each address antifuse circuit outputting an address fuse signal according to a program state of an antifuse included in the corresponding address antifuse circuit, an address comparator including a plurality of address comparison signal generators, each address comparison signal generator combining a first test signal for determining an initial defect of the antifuse and a corresponding bit of an externally applied address signal to generate a test address, and comparing the test address with the address fuse signal to generate an address comparison signal, and a redundant enable signal generator for enabling a redundancy enable signal in response to a plurality of address comparison signals.

摘要翻译： 一种半导体存储器件，包括一个包括多个地址反熔丝电路的保险丝盒，每个地址反熔丝电路根据相应的地址反熔丝电路中包括的反熔丝的编程状态输出地址熔丝信号，地址比较器包括多个地址比较 信号发生器，每个地址比较信号发生器组合用于确定反熔丝的初始缺陷的第一测试信号和外部施加的地址信号的相应位以产生测试地址，以及将测试地址与地址熔丝信号进行比较，以产生 地址比较信号，以及冗余使能信号发生器，用于响应于多个地址比较信号启用冗余使能信号。

公开(公告)号：US20080082870A1

公开(公告)日：2008-04-03

申请号：US11902261

申请日：2007-09-20

申请人： Bok-gue Park

发明人： Bok-gue Park

IPC分类号： G06F11/00

CPC分类号： G06F11/1008

摘要： Example embodiments are directed to a parallel bit test device and method using error correcting code. The parallel bit test device may include an error detecting and correcting unit configured to count the number of fail bits in an m-bit data signal, for example, by comparing bits of the m-bit data signal with corresponding bits of expected data, where m is a positive integer, and to output correction signals. The error detecting and correcting unit may be further configured to perform at least one logic operation on a correction control signal and comparison signals. The correction control signal may be generated in response to a test mode register set (TMRS) signal set and input by a user such that the logic level of the correction control signal may vary according to the counted number of fail bits. Each comparison signal may include information about a fail bit and the address of the fail bit.

摘要翻译： 示例性实施例涉及使用纠错码的并行位测试装置和方法。 并行比特测试装置可以包括错误检测和校正单元，其被配置为对m比特数据信号中的失败比特数进行计数，例如通过比较m比特数据信号的比特与预期数据的相应比特，其中 m是正整数，并输出校正信号。 误差检测和校正单元还可以被配置为对校正控制信号和比较信号执行至少一个逻辑运算。 校正控制信号可以响应于由用户设置并输入的测试模式寄存器组（TMRS）信号产生，使得校正控制信号的逻辑电平可以根据计数的失败位数而变化。 每个比较信号可以包括关于故障位和故障位的地址的信息。