公开(公告)号：US20090079496A1

公开(公告)日：2009-03-26

申请号：US12238894

申请日：2008-09-26

Applicant: Byung-Se SO ,  Dong-Ho LEE ,  Hyun-Soon JANG

Inventor： Byung-Se SO ,  Dong-Ho LEE ,  Hyun-Soon JANG

IPC: H01L25/00 ,  H05K7/00

CPC classification number: H01L24/49 ,  G11C5/00 ,  G11C5/06 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

Abstract translation: 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。 此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。

公开(公告)号：US20090044063A1

公开(公告)日：2009-02-12

申请号：US11974342

申请日：2007-10-12

Applicant: Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

Inventor： Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G11C29/56 ,  G11C29/56008 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.

Abstract translation: 半导体存储器件包括存储器核心单元，N个数据输出缓冲器，N个数据输出端口以及多个测试逻辑电路。 存储核心单元通过N条数据线存储测试数据。 N个数据输出缓冲器分别连接到相应的N个数据线。 N个数据输出端口连接到相应的N个数据输出缓冲器，并分别与外部测试仪交换测试数据。 多个测试逻辑电路通过来自N条数据线的K条数据线接收测试数据，对所接收的测试数据进行测试逻辑运算，并提供一个数据输出缓冲器控制信号，该信号确定N个数据输出缓冲器的激活 测试模式下的数据输出缓冲区。 半导体存储器件降低了测试周期。

公开(公告)号：US5999031A

公开(公告)日：1999-12-07

申请号：US683376

申请日：1996-07-18

Applicant: Hyun-soon Jang

Inventor： Hyun-soon Jang

IPC: G11C11/417 ,  G06F3/00 ,  G06F13/16 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0948 ,  H03H11/26

CPC classification number: H03K19/01721

Abstract: A semiconductor device is provided having an input driver and an output receiver connected by a bus line, the bus line including pulse generating and driver circuitry responsive to threshold levels of voltage change so as to perform high speed switching which compensates for the load of the bus line.

Abstract translation: 提供了一种半导体器件，其具有通过总线连接的输入驱动器和输出接收器，该总线包括响应阈值电压变化的脉冲产生和驱动器电路，从而执行补偿总线负载的高速切换 线。

公开(公告)号：US5812475A

公开(公告)日：1998-09-22

申请号：US770845

申请日：1996-12-20

Applicant: Sang-Kil Lee ,  Hyun-Soon Jang

Inventor： Sang-Kil Lee ,  Hyun-Soon Jang

IPC: G11C11/403 ,  G11C11/401 ,  G11C11/406 ,  G11C7/00

CPC classification number: G11C11/406

Abstract: A self refresh circuit for an integrated circuit memory device includes a programmable refresh circuit, a plurality of counters, and a refresh cycle selection circuit. The programmable refresh circuit can be electrically programmed to generate one of a plurality of refresh control signals. A first one of the counters generates a first oscillating output signal having a first predetermined period and each successive counter generates a respective oscillating output signal having a respective period twice that of a respective preceding counter. The refresh cycle selection circuit selects a self refresh cycle from one of the oscillating output signals in response to the refresh control signal generated by the at least one programmable refresh circuit. Related methods are also disclosed.

Abstract translation: 用于集成电路存储器件的自刷新电路包括可编程刷新电路，多个计数器和刷新周期选择电路。 可编程刷新电路可以被电编程以产生多个刷新控制信号中的一个。 第一个计数器产生具有第一预定周期的第一振荡输出信号，并且每个连续的计数器产生相应的振荡输出信号，该振荡输出信号的相应周期是相应的前一个计数器的两倍。 刷新周期选择电路响应于由至少一个可编程刷新电路产生的刷新控制信号，从振荡输出信号中的一个选择自刷新周期。 还公开了相关方法。

公开(公告)号：US5663913A

公开(公告)日：1997-09-02

申请号：US638373

申请日：1996-04-26

Applicant: Ho-Cheol Lee ,  Hyun-Soon Jang

Inventor： Ho-Cheol Lee ,  Hyun-Soon Jang

IPC: G11C11/41 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C7/22

Abstract: A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.

Abstract translation: 半导体存储器件通过向并行总线中的各个传输线路中的各个传输线路添加相应的负载传输线而使并行传输总线的各个传输线之间的偏移最小化。 在芯片内与预定区域相邻地形成包括用于产生内部控制信号的第一并联的内部电路组的第一电路单元。 第二电路单元包括用于响应于第一电路单元的输出执行预定操作的第二并联的内部电路组。 第二电路通过由分别连接在第一和第二电路单元的各个内部电路之间的多条传输线组成的并行总线向第一电路发送信号。 多个负载传输线分别连接到各个传输线的预定部分，从而均衡传输线的负载。

公开(公告)号：US5590086A

公开(公告)日：1996-12-31

申请号：US580481

申请日：1995-12-29

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5485426A

公开(公告)日：1996-01-16

申请号：US289583

申请日：1994-08-15

Applicant: Si-Yeol Lee ,  Hyun-Soon Jang ,  Myung-Ho Kim

Inventor： Si-Yeol Lee ,  Hyun-Soon Jang ,  Myung-Ho Kim

IPC: G11C11/41 ,  G11C7/10 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C11/4096 ,  G11C7/1048 ,  G11C7/18

Abstract: A semiconductor memory device for alternately selecting two groups of input/output lines according to a predetermined column address. A first group of a number of the input/output line pairs is driven by activation of any one of the selection signals within the first group, and a second group of a number of the input/output line pairs is driven by activation of any one of the selection signals within the second group. Furthermore, the input/output line pairs within the second group are precharged and equalized when the input/output line pairs within the first group are driven, and the input/output line pairs within the first group are precharged and equalized when the input/output line pairs within the second group are driven.

Abstract translation: 一种用于根据预定的列地址交替地选择两组输入/输出线的半导体存储器件。 通过激活第一组内的任一个选择信号来驱动多个输入/输出线对中的第一组，并且多个输入/输出线对的第二组由任何一个的激活驱动 的第二组内的选择信号。 此外，当第一组中的输入/输出线对被驱动时，第二组内的输入/输出线对被预先充电和均衡，并且当输入/输出时第一组内的输入/输出线对被预先充电和均衡 驱动第二组内的线对。

公开(公告)号：US5355033A

公开(公告)日：1994-10-11

申请号：US726188

申请日：1991-07-05

Applicant: Hyun-Soon Jang

Inventor： Hyun-Soon Jang

IPC: G11C11/417 ,  G05F3/24 ,  G11C11/409 ,  G11C11/413 ,  H03K19/0185 ,  H03K19/0175 ,  H03K19/0948

CPC classification number: H03K19/018521 ,  G05F3/24

Abstract: The invention is to provide a data input buffer which can attain stably an input trip level regardless of a variation of power source voltage, for use in a semiconductor memory device, and particularly to provide a data input buffer which is not affected by a variation of power source voltage. The data input buffer circuit comprises a conductive passage, coupled between the power source voltage and a level sensing node, for adjusting the amount of an current according to a level of input voltage; and an insulation gate field effect transistor, with one end of channel of the transistor connected to the conductive passage, other end of channel of the transistor connected to ground voltage terminal and a gate of the transistor to which voltage is applied according to a level of the power source voltage.

Abstract translation: 本发明是提供一种数据输入缓冲器，其可以稳定地获得输入跳闸电平，而不管电源电压的变化如何，用于半导体存储器件中，特别是提供不受变化影响的数据输入缓冲器 电源电压。 数据输入缓冲电路包括耦合在电源电压和电平感测节点之间的导电通道，用于根据输入电压的电平来调节电流量; 以及绝缘栅场效应晶体管，晶体管的一端连接到导电通道，晶体管的另一端连接到接地电压端子，并且晶体管的栅极根据电压的电平施加电压 电源电压。

公开(公告)号：US08902673B2

公开(公告)日：2014-12-02

申请号：US13439271

申请日：2012-04-04

Applicant: Hong-Beom Kim ,  Hyun-Soon Jang

Inventor： Hong-Beom Kim ,  Hyun-Soon Jang

IPC: G11C7/10 ,  G11C29/02 ,  G11C29/12 ,  G11C29/48

CPC classification number: G11C29/022 ,  G11C29/1201 ,  G11C29/48

Abstract: A method of testing a semiconductor memory device includes writing first data to a memory cell array in the semiconductor memory device, loading second data from the memory cell array onto a plurality of data pads of the semiconductor memory device, rewriting the second data to the memory cell array, and outputting test result data through one or more test pads. The first data is received from an external device through the one or more test pads, which correspond to one or more of the plurality of data pads. The test result data is based on the rewritten data in the memory cell array.

Abstract translation: 一种测试半导体存储器件的方法包括将第一数据写入半导体存储器件中的存储单元阵列，将来自存储单元阵列的第二数据加载到半导体存储器件的多个数据焊盘上，将第二数据重新写入存储器 单元阵列，并通过一个或多个测试垫输出测试结果数据。 第一数据通过一个或多个测试焊盘从外部设备接收，该测试焊盘对应于多个数据焊盘中的一个或多个。 测试结果数据基于存储单元阵列中的重写数据。

公开(公告)号：US20120257461A1

公开(公告)日：2012-10-11

申请号：US13439271

申请日：2012-04-04

Applicant: Hong-Beom KIM ,  Hyun-Soon JANG

Inventor： Hong-Beom KIM ,  Hyun-Soon JANG

IPC: G11C7/10 ,  G11C29/00

CPC classification number: G11C29/022 ,  G11C29/1201 ,  G11C29/48

Abstract: A method of testing a semiconductor memory device includes writing first data to a memory cell array in the semiconductor memory device, loading second data from the memory cell array onto a plurality of data pads of the semiconductor memory device, rewriting the second data to the memory cell array, and outputting test result data through one or more test pads. The first data is received from an external device through the one or more test pads, which correspond to one or more of the plurality of data pads. The test result data is based on the rewritten data in the memory cell array.

Abstract translation: 一种测试半导体存储器件的方法包括将第一数据写入半导体存储器件中的存储单元阵列，将来自存储单元阵列的第二数据加载到半导体存储器件的多个数据焊盘上，将第二数据重新写入存储器 单元阵列，并通过一个或多个测试垫输出测试结果数据。 第一数据通过一个或多个测试焊盘从外部设备接收，该测试焊盘对应于多个数据焊盘中的一个或多个。 测试结果数据基于存储单元阵列中的重写数据。