公开(公告)号：US07375373B2

公开(公告)日：2008-05-20

申请号：US10482256

申请日：2002-07-02

申请人： Jae-Gab Lee ,  Bong-Joo Kang ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Jae-Gab Lee ,  Bong-Joo Kang ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L21/00 ,  H01L27/01 ,  H01L21/84

CPC分类号： H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

摘要翻译： 薄膜晶体管阵列面板包括绝缘基板，形成在绝缘基板上的栅极线。 栅极绝缘层覆盖栅极线。 在栅极绝缘层上形成半导体图形。 在栅极绝缘层和半导体图案上形成具有源电极，漏电极和数据线的数据线。 在数据线上形成保护层。 在保护层上形成通过接触孔与漏电极连接的像素电极。 栅极线和数据线由含有Ag的Ag合金和包含选自Zn，In，Sn和Cr中的至少一种的添加剂制成。

公开(公告)号：US07276731B2

公开(公告)日：2007-10-02

申请号：US11053833

申请日：2005-02-10

申请人： Chang-Oh Jeong ,  Bong-Joo Kang ,  Jae-Gab Lee

发明人： Chang-Oh Jeong ,  Bong-Joo Kang ,  Jae-Gab Lee

IPC分类号： H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L23/53242 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer based on silicon nitride or an organic material is deposited onto the substrate, and patterned through dry etching such that the protective layer bears contact holes exposing the drain electrodes, the gate pads and the data pads, respectively. An indium zinc oxide or indium tin oxide-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, and subsidiary gate and data pads. The pixel electrodes are electrically connected to the drain electrodes, and the subsidiary gate and data pads to the gate and data pads.

摘要翻译： 在制造薄膜晶体管阵列基板的方法中，玻璃基板进行氧等离子体处理。 将银或银合金基导电层沉积到衬底上，并被图案化，从而形成在水平方向上进行的栅极线组件。 栅极线组件包括栅极线，栅电极和栅极焊盘。 此后，在衬底上沉积氮化硅基栅极绝缘层，并且在栅极绝缘层上依次形成半导体层和欧姆接触层。 对半导体层和欧姆接触层进行HF处理。 将银合金基导电层沉积到衬底上，并被图案化从而形成数据线组件。 数据线组件包括跨越栅极线，源电极，漏电极和数据焊盘的数据线。 基于氮化硅或有机材料的保护层沉积到衬底上，并通过干蚀刻图案化，使得保护层分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 将氧化铟锌或铟锡氧化物基层沉积在衬底上，并被图案化，从而形成像素电极，以及辅助栅极和数据焊盘。 像素电极电连接到漏电极，辅助栅极和数据焊盘电连接到栅极和数据焊盘。

公开(公告)号：US07883942B2

公开(公告)日：2011-02-08

申请号：US11875199

申请日：2007-10-19

申请人： Bum-Gee Baek ,  Kwon-Young Choi ,  Young-Joon Rhee ,  Bong-Joo Kang ,  Seung-Taek Lim ,  Hyang-Shik Kong ,  Won-Joo Kim

发明人： Bum-Gee Baek ,  Kwon-Young Choi ,  Young-Joon Rhee ,  Bong-Joo Kang ,  Seung-Taek Lim ,  Hyang-Shik Kong ,  Won-Joo Kim

IPC分类号： H01L21/00

CPC分类号： G02F1/13458 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908

摘要： Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

摘要翻译： 栅极线形成在基板上。 依次沉积栅极绝缘层，本征a-Si层，外部a-Si层，下部Cr膜和含Al金属的上部膜。 在上部膜上形成具有较粗的第一部分在导线区域上的光刻胶和在沟道区域上较薄的第二部分的光致抗蚀剂。 在其余区域上的上部膜被湿式蚀刻，并且其余区域上的下部膜和a-Si层与光致抗蚀剂的第二部分一起被干蚀刻。 除去沟道区上的上膜，下膜和非本征a-Si层。 通过湿蚀刻来进行通道区域上的上膜和下膜的去除，并且在去除沟道区上的上膜之后去除光致抗蚀剂的第一部分。

公开(公告)号：US06867108B2

公开(公告)日：2005-03-15

申请号：US10112760

申请日：2002-04-02

申请人： Chang-Oh Jeong ,  Bong-Joo Kang ,  Jae-Gab Lee

发明人： Chang-Oh Jeong ,  Bong-Joo Kang ,  Jae-Gab Lee

IPC分类号： G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L23/52 ,  H01L23/532 ,  H01L27/12 ,  H01L29/43 ,  H01L29/49 ,  H01L29/786 ,  H01L21/20 ,  H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L23/53242 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer based on silicon nitride or an organic material is deposited onto the substrate, and patterned through dry etching such that the protective layer bears contact holes exposing the drain electrodes, the gate pads and the data pads, respectively. An indium zinc oxide or indium tin oxide-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, and subsidiary gate and data pads. The pixel electrodes are electrically connected to the drain electrodes, and the subsidiary gate and data pads to the gate and data pads.

摘要翻译： 在制造薄膜晶体管阵列基板的方法中，玻璃基板进行氧等离子体处理。 将银或银合金基导电层沉积到衬底上，并被图案化，从而形成在水平方向上进行的栅极线组件。 栅极线组件包括栅极线，栅电极和栅极焊盘。 此后，在衬底上沉积氮化硅基栅极绝缘层，并且在栅极绝缘层上依次形成半导体层和欧姆接触层。 对半导体层和欧姆接触层进行HF处理。 将银合金基导电层沉积到衬底上，并被图案化从而形成数据线组件。 数据线组件包括跨越栅极线，源电极，漏电极和数据焊盘的数据线。 基于氮化硅或有机材料的保护层沉积到衬底上，并通过干蚀刻图案化，使得保护层分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 将氧化铟锌或铟锡氧化物基层沉积在衬底上，并被图案化，从而形成像素电极，以及辅助栅极和数据焊盘。 像素电极电连接到漏电极，辅助栅极和数据焊盘电连接到栅极和数据焊盘。

公开(公告)号：US07294855B2

公开(公告)日：2007-11-13

申请号：US10653556

申请日：2003-09-02

申请人： Bum-Gee Baek ,  Kwon-Young Choi ,  Young-Joon Rhee ,  Bong-Joo Kang ,  Seung-Taek Lim ,  Hyang-Shik Kong ,  Won-Joo Kim

发明人： Bum-Gee Baek ,  Kwon-Young Choi ,  Young-Joon Rhee ,  Bong-Joo Kang ,  Seung-Taek Lim ,  Hyang-Shik Kong ,  Won-Joo Kim

IPC分类号： H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908

摘要： Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

摘要翻译： 栅极线形成在基板上。 依次沉积栅极绝缘层，本征a-Si层，外部a-Si层，下部Cr膜和含Al金属的上部膜。 在上部膜上形成具有较粗的第一部分在导线区域上的光刻胶和在沟道区域上较薄的第二部分的光致抗蚀剂。 在其余区域上的上部膜被湿式蚀刻，并且其余区域上的下部膜和a-Si层与光致抗蚀剂的第二部分一起被干蚀刻。 除去沟道区上的上膜，下膜和非本征a-Si层。 通过湿蚀刻来进行通道区域上的上膜和下膜的去除，并且在去除沟道区上的上膜之后去除光致抗蚀剂的第一部分。

公开(公告)号：US20080227245A1

公开(公告)日：2008-09-18

申请号：US12112104

申请日：2008-04-30

申请人： Jae-Gab LEE ,  Bong-Joo KANG ,  Beom-Seok CHO ,  Chang-Oh JEONG

发明人： Jae-Gab LEE ,  Bong-Joo KANG ,  Beom-Seok CHO ,  Chang-Oh JEONG

IPC分类号： H01L21/84

CPC分类号： H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

摘要翻译： 薄膜晶体管阵列面板包括绝缘基板，形成在绝缘基板上的栅极线。 栅极绝缘层覆盖栅极线。 在栅极绝缘层上形成半导体图形。 在栅极绝缘层和半导体图案上形成具有源电极，漏电极和数据线的数据线。 在数据线上形成保护层。 在保护层上形成通过接触孔与漏电极连接的像素电极。 栅极线和数据线由含有Ag的Ag合金和包含选自Zn，In，Sn和Cr中的至少一种的添加剂制成。

公开(公告)号：US20080044996A1

公开(公告)日：2008-02-21

申请号：US11875199

申请日：2007-10-19

申请人： Bum-Gee BAEK ,  Kwon-Young CHOI ,  Young-Joon RHEE ,  Bong-Joo KANG ,  Seung-Taek LIM ,  Hyang-Shik KONG ,  Won-Joo KIM

发明人： Bum-Gee BAEK ,  Kwon-Young CHOI ,  Young-Joon RHEE ,  Bong-Joo KANG ,  Seung-Taek LIM ,  Hyang-Shik KONG ,  Won-Joo KIM

IPC分类号： H01L21/44

CPC分类号： G02F1/13458 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908

摘要： Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a—Si layer, an extrinsic a—Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a—Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a—Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

摘要翻译： 栅极线形成在基板上。 依次沉积栅极绝缘层，本征a-Si层，外部a-Si层，下部Cr膜和含Al金属的上部膜。 在上部膜上形成具有较粗的第一部分在导线区域上的光刻胶和在沟道区域上较薄的第二部分的光致抗蚀剂。 在其余区域上的上部膜被湿式蚀刻，并且其余区域上的下部膜和a-Si层与光致抗蚀剂的第二部分一起被干蚀刻。 除去沟道区上的上膜，下膜和非本征a-Si层。 通过湿蚀刻来进行通道区域上的上膜和下膜的去除，并且在去除沟道区上的上膜之后去除光致抗蚀剂的第一部分。

公开(公告)号：US20050145844A1

公开(公告)日：2005-07-07

申请号：US11053833

申请日：2005-02-10

申请人： Chang-Oh Jeong ,  Bong-Joo Kang ,  Jae-Gab Lee

发明人： Chang-Oh Jeong ,  Bong-Joo Kang ,  Jae-Gab Lee

IPC分类号： G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L23/52 ,  H01L23/532 ,  H01L27/12 ,  H01L29/43 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L23/53242 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer based on silicon nitride or an organic material is deposited onto the substrate, and patterned through dry etching such that the protective layer bears contact holes exposing the drain electrodes, the gate pads and the data pads, respectively. An indium zinc oxide or indium tin oxide-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, and subsidiary gate and data pads. The pixel electrodes are electrically connected to the drain electrodes, and the subsidiary gate and data pads to the gate and data pads.

公开(公告)号：US07608494B2

公开(公告)日：2009-10-27

申请号：US12112104

申请日：2008-04-30

申请人： Jae-Gab Lee ,  Bong-Joo Kang ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Jae-Gab Lee ,  Bong-Joo Kang ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L21/84

CPC分类号： H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

摘要翻译： 薄膜晶体管阵列面板包括绝缘基板，形成在绝缘基板上的栅极线。 栅极绝缘层覆盖栅极线。 在栅极绝缘层上形成半导体图形。 在栅极绝缘层和半导体图案上形成具有源电极，漏电极和数据线的数据线。 在数据线上形成保护层。 在保护层上形成通过接触孔与漏电极连接的像素电极。 栅极线和数据线由含有Ag的Ag合金和包含选自Zn，In，Sn和Cr中的至少一种的添加剂制成。