公开(公告)号：US07883942B2

公开(公告)日：2011-02-08

申请号：US11875199

申请日：2007-10-19

申请人： Bum-Gee Baek ,  Kwon-Young Choi ,  Young-Joon Rhee ,  Bong-Joo Kang ,  Seung-Taek Lim ,  Hyang-Shik Kong ,  Won-Joo Kim

发明人： Bum-Gee Baek ,  Kwon-Young Choi ,  Young-Joon Rhee ,  Bong-Joo Kang ,  Seung-Taek Lim ,  Hyang-Shik Kong ,  Won-Joo Kim

IPC分类号： H01L21/00

CPC分类号： G02F1/13458 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908

摘要： Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

摘要翻译： 栅极线形成在基板上。 依次沉积栅极绝缘层，本征a-Si层，外部a-Si层，下部Cr膜和含Al金属的上部膜。 在上部膜上形成具有较粗的第一部分在导线区域上的光刻胶和在沟道区域上较薄的第二部分的光致抗蚀剂。 在其余区域上的上部膜被湿式蚀刻，并且其余区域上的下部膜和a-Si层与光致抗蚀剂的第二部分一起被干蚀刻。 除去沟道区上的上膜，下膜和非本征a-Si层。 通过湿蚀刻来进行通道区域上的上膜和下膜的去除，并且在去除沟道区上的上膜之后去除光致抗蚀剂的第一部分。

公开(公告)号：US07294855B2

公开(公告)日：2007-11-13

申请号：US10653556

申请日：2003-09-02

申请人： Bum-Gee Baek ,  Kwon-Young Choi ,  Young-Joon Rhee ,  Bong-Joo Kang ,  Seung-Taek Lim ,  Hyang-Shik Kong ,  Won-Joo Kim

发明人： Bum-Gee Baek ,  Kwon-Young Choi ,  Young-Joon Rhee ,  Bong-Joo Kang ,  Seung-Taek Lim ,  Hyang-Shik Kong ,  Won-Joo Kim

IPC分类号： H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908

摘要： Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

摘要翻译： 栅极线形成在基板上。 依次沉积栅极绝缘层，本征a-Si层，外部a-Si层，下部Cr膜和含Al金属的上部膜。 在上部膜上形成具有较粗的第一部分在导线区域上的光刻胶和在沟道区域上较薄的第二部分的光致抗蚀剂。 在其余区域上的上部膜被湿式蚀刻，并且其余区域上的下部膜和a-Si层与光致抗蚀剂的第二部分一起被干蚀刻。 除去沟道区上的上膜，下膜和非本征a-Si层。 通过湿蚀刻来进行通道区域上的上膜和下膜的去除，并且在去除沟道区上的上膜之后去除光致抗蚀剂的第一部分。

公开(公告)号：US20090285030A1

公开(公告)日：2009-11-19

申请号：US11335618

申请日：2006-01-20

申请人： Dong-Hun Kang ,  Jeong-Hee Han ,  Wan-Jun Park ,  Won-Joo Kim ,  Jae-Woong Hyun

发明人： Dong-Hun Kang ,  Jeong-Hee Han ,  Wan-Jun Park ,  Won-Joo Kim ,  Jae-Woong Hyun

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C11/56 ,  G11C2213/17 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/938 ,  Y10S977/943

摘要： A memory device may include a channel including at least one carbon nanotube. A source and a drain may be arranged at opposing ends of the channel and may contact different parts of the channel. A first storage node may be formed under the channel, and a second storage node may be formed on the channel. A first gate electrode may be formed under the first storage node and a second gate electrode may be formed on the second storage node.

摘要翻译： 存储器件可以包括包括至少一个碳纳米管的通道。 源极和漏极可以布置在通道的相对端处并且可以接触通道的不同部分。 可以在信道下形成第一存储节点，并且可以在信道上形成第二存储节点。 第一栅电极可以形成在第一存储节点下方，并且第二栅电极可以形成在第二存储节点上。

公开(公告)号：US07507674B2

公开(公告)日：2009-03-24

申请号：US11270565

申请日：2005-11-10

申请人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

发明人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

IPC分类号： H01L21/461

CPC分类号： H01L27/24 ,  Y10S438/947

摘要： A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise) a conductive material layer, a diode layer and a data storage layer on a bottom layer, forming a first material layer on the data storage layer, forming a first hole exposing the data storage layer in the first material layer, forming a first spacer with a second material layer on the sidewall of the first hole, filling the first hole with a third material layer and covering the first spacer; removing the first material layer, forming a second spacer with a fourth material layer on the sidewall of the first spacer; removing the third material layer, and forming a second hole exposing the bottom layer in a first stack structure using the first and second spacers as a mask. These operations may result in the formation of bit lines and word lines as described.

摘要翻译： 提供一种用于制造包括根据本发明的示例性实施例的作为存储节点的电阻变化层的存储器件的方法和由该方法制造的存储器件。 根据本发明的示例性实施例，该方法可以包括在底层上层叠（顺序地或以其他方式）导电材料层，二极管层和数据存储层，在数据存储层上形成第一材料层，形成 第一孔暴露第一材料层中的数据存储层，在第一孔的侧壁上形成具有第二材料层的第一间隔物，用第三材料层填充第一孔并覆盖第一间隔物; 去除所述第一材料层，在所述第一间隔物的侧壁上形成具有第四材料层的第二间隔物; 去除第三材料层，并且使用第一和第二间隔件作为掩模，形成以第一堆叠结构暴露底层的第二孔。 这些操作可能导致如所描述的位线和字线的形成。

公开(公告)号：US20080191264A1

公开(公告)日：2008-08-14

申请号：US12010139

申请日：2008-01-22

申请人： Won-Joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： Won-Joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： H01L29/00 ,  H01L21/3205

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Non-volatile memory devices highly integrated using an oxide based compound semiconductor and methods of operating and fabricating the same are provided. A non-volatile memory device may include one or more oxide based compound semiconductor layers. A plurality of auxiliary gate electrodes may be arranged to be insulated from the one or more oxide based compound semiconductor layers. A plurality of control gate electrodes may be positioned between adjacent pairs of the plurality of auxiliary gate electrodes at a different level from the plurality of auxiliary gate electrodes. The plurality of control gate electrodes may be insulated from the one or more oxide based compound semiconductor layers. A plurality of charge storing layers may be interposed between the one or more oxide based compound semiconductor layers and the plurality of control gate electrodes.

摘要翻译： 提供了使用基于氧化物的化合物半导体高度集成的非易失性存储器件及其操作和制造方法。 非易失性存储器件可以包括一个或多个基于氧化物的化合物半导体层。 多个辅助栅极电极可以布置成与一个或多个氧化物基化合物半导体层绝缘。 多个控制栅电极可以位于与多个辅助栅极电极不同的多个辅助栅电极的相邻对之间。 多个控制栅电极可以与一个或多个氧化物基化合物半导体层绝缘。 可以在一个或多个氧化物基化合物半导体层和多个控制栅电极之间插入多个电荷存储层。

公开(公告)号：US20070285798A1

公开(公告)日：2007-12-13

申请号：US11889511

申请日：2007-08-14

申请人： Seung-Hyuk Chang ,  I-Hun Song ,  Won-Joo Kim ,  Suk-Pil Kim ,  Hoon Kim

发明人： Seung-Hyuk Chang ,  I-Hun Song ,  Won-Joo Kim ,  Suk-Pil Kim ,  Hoon Kim

IPC分类号： G02B9/00 ,  B01J19/08 ,  G03F7/20

CPC分类号： G03F7/70233

摘要： Off-axis projection optics that includes first and second mirrors positioned off-axis and sharing a confocal point that are arranged to reduce linear astigmatism. If a distance between an object plane and the first mirror is l1, an incident angle of light coming from the object plane to the first mirror is i1, a distance between the first mirror and the confocal point is l1′, a distance between the confocal point and the second mirror is l2, an incident angle of light coming from the first mirror to the second mirror is i2, and a distance between the second mirror and an image plane is l2′, the off-axis projection optics may satisfy the following equation: l 1 ′ + l 1 l 1 ⁢ tan ⁢   ⁢ i 1 = l 2 ′ + l 2 l 2 ⁢ tan ⁢   ⁢ i 2 .

公开(公告)号：US20070222036A1

公开(公告)日：2007-09-27

申请号：US11723490

申请日：2007-03-20

申请人： Yoon-Dong Park ,  Suk-PiI Kim ,  Won-Joo Kim

发明人： Yoon-Dong Park ,  Suk-PiI Kim ,  Won-Joo Kim

IPC分类号： H01L29/06

CPC分类号： H01L27/105 ,  H01L27/101 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1159 ,  H01L27/24 ,  H01L29/785

摘要： A semiconductor memory device and methods of manufacturing and operating the same may be provided. The semiconductor memory device may include a substrate, at least a pair of fins protruding from the semiconductor substrate and facing each other with a gap between fins of the pair of fins, an insulating layer formed between the pair of the fins, a storage node formed on the pair of fins and/or a surface of a portion of the insulating layer, and/or a gate electrode formed on the storage node.

摘要翻译： 可以提供半导体存储器件及其制造和操作的方法。 半导体存储器件可以包括基板，至少一对翅片，其从半导体基板突出并且彼此面对，具有在所述一对翅片的翅片之间的间隙;形成在所述一对翅片之间的绝缘层，形成的存储节点 在所述一对翅片和/或所述绝缘层的一部分的表面上，和/或形成在所述存储节点上的栅电极。

公开(公告)号：US20060110877A1

公开(公告)日：2006-05-25

申请号：US11270565

申请日：2005-11-10

申请人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

发明人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

IPC分类号： H01L21/8244

CPC分类号： H01L27/24 ,  Y10S438/947

摘要： A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise) a conductive material layer, a diode layer and a data storage layer on a bottom layer, forming a first material layer on the data storage layer, forming a first hole exposing the data storage layer in the first material layer, forming a first spacer with a second material layer on the sidewall of the first hole, filling the first hole with a third material layer and covering the first spacer; removing the first material layer, forming a second spacer with a fourth material layer on the sidewall of the first spacer; removing the third material layer, and forming a second hole exposing the bottom layer in a first stack structure using the first and second spacers as a mask. These operations may result in the formation of bit lines and word lines as described.

公开(公告)号：US06525462B1

公开(公告)日：2003-02-25

申请号：US09275522

申请日：1999-03-24

申请人： Won-Joo Kim

发明人： Won-Joo Kim

IPC分类号： H01J190

CPC分类号： H01J31/123 ,  G09G3/22 ,  H01J9/185 ,  H01J9/242 ,  H01J29/028 ,  H01J29/864 ,  H01J2329/863 ,  H01J2329/864 ,  H01J2329/8655

摘要： A display includes a baseplate and an emitter formed on the baseplate. The display also includes a faceplate having a cathodoluminescent coating on a surface facing the baseplate and the emitter. A plurality of spacers separate the faceplate and the baseplate to prevent bowing of the faceplate or the baseplate towards each other. The spacers are formed from silicon, simplifying field emission device assembly and resulting in a superior display.

公开(公告)号：US06491561B2

公开(公告)日：2002-12-10

申请号：US10053170

申请日：2001-11-02

申请人： Won-Joo Kim

发明人： Won-Joo Kim

IPC分类号： H01J900

CPC分类号： H01J31/123 ,  G09G3/22 ,  H01J9/185 ,  H01J9/242 ,  H01J29/028 ,  H01J29/864 ,  H01J2329/863 ,  H01J2329/864 ,  H01J2329/8655

摘要： Methods of manufacturing faceplates for field emission displays are disclosed. In one embodiment, a method for manufacturing a faceplate includes forming a transparent conductive layer on a transparent viewing screen, forming an insulating layer on the transparent conductive layer, anodically bonding silicon to the insulating layer, directionally etching the silicon to form isolated regions of silicon on the insulating layer, and etching the insulating layer using the isolated regions of silicon as a mask.

摘要翻译： 公开了用于场致发射显示器的面板的制造方法。 在一个实施例中，一种用于制造面板的方法包括在透明观察屏幕上形成透明导电层，在透明导电层上形成绝缘层，将硅阳极结合到绝缘层，定向蚀刻硅以形成硅的隔离区域 并且使用硅的孤立区域作为掩模来蚀刻绝缘层。