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    Chemical vapor deposition of tungsten using nitrogen-containing gas
    3.
    发明授权
    Chemical vapor deposition of tungsten using nitrogen-containing gas 失效
    使用含氮气体化学气相沉积钨

    公开(公告)号：US06211082B1

    公开(公告)日：2001-04-03

    申请号：US09021462

    申请日：1998-02-10

    申请人： Bong-young Yoo ,  Byung-Lyul Park ,  Dae-hong Ko ,  Sang-in Lee

    发明人： Bong-young Yoo ,  Byung-Lyul Park ,  Dae-hong Ko ,  Sang-in Lee

    IPC分类号： H01L2144

    CPC分类号： C23C16/08 ,  H01L21/28568

    摘要： A tungsten or other metal layer is chemical vapor deposited using a source gas containing tungsten, a reducing gas and a nitrogen-containing gas. The nitrogen-containing gas can act as a surface roughness reducing gas that reduces the roughness of the tungsten layer compared to a tungsten layer that is chemical vapor deposited using the source gas containing tungsten and the reducing gas, but without using the surface roughness reducing gas. Viewed in another way, the nitrogen-containing gas acts as a growth rate controlling gas that produces uniform growth of the tungsten layer in a plurality of directions compared to a tungsten layer that is deposited using the source gas containing tungsten and the reducing gas, but without using the growth rate controlling gas.

    摘要翻译： 使用含有钨，还原气体和含氮气体的源气体化学气相沉积钨或其它金属层。 与使用含有钨和还原气体的源气体进行化学气相沉积的钨层相比，含氮气体可以用作表面粗糙度降低气体，其降低钨层的粗糙度，但不使用表面粗糙度还原气体 。 以另一种方式看，与使用含钨和还原气体的源气体沉积的钨层相比，含氮气体充当生长速率控制气体，其产生钨层在多个方向上的均匀生长，但是 而不用生长速率控制气体。

    Methods of forming electrical interconnects on semiconductor substrates
    4.
    发明授权
    Methods of forming electrical interconnects on semiconductor substrates 失效
    在半导体衬底上形成电互连的方法

    公开(公告)号：US5863835A

    公开(公告)日：1999-01-26

    申请号：US906718

    申请日：1997-08-05

    申请人： Bong-Young Yoo ,  Si-Young Choi

    发明人： Bong-Young Yoo ,  Si-Young Choi

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L21/76885 ,  H01L21/76807 ,  H01L23/5226 ,  H01L2924/0002

    摘要： Methods of forming electrical interconnects on semiconductor substrates include the steps of forming a first electrically insulating layer (e.g., silicon dioxide) and then forming a contact hole in the insulating layer to expose a layer underlying the insulating layer. A first electrically conductive region (e.g., W, Ti, Tin, Al) is then formed in the contact hole. A step is then performed to remove a portion of the first electrically insulating layer to define a recess therein which preferably surrounds an upper portion of the first conductive region. A second electrically conductive region (e.g., Al, Cu, W, Ti, Ta and Co) is then formed in the recess. Here, the first conductive region is preferably chosen to have good step coverage capability to fully bury the contact hole and the second conductive region is preferably chosen to have very low resistance even if some degree of step coverage capability is sacrificed. Planarization steps (e.g, CMP, etch-back) may also be performed to define the first conductive region in the contact hole and define the second conductive region in the recess surrounding the first conductive region. Barrier metal layers may also be conformable deposited in the contact hole prior to forming the first conductive region therein and in the recess prior to forming the second conductive region therein.

    摘要翻译： 在半导体衬底上形成电互连的方法包括以下步骤：形成第一电绝缘层（例如二氧化硅），然后在绝缘层中形成接触孔以暴露绝缘层下面的层。 然后在接触孔中形成第一导电区域（例如，W，Ti，Tin，Al）。 然后执行步骤以去除第一电绝缘层的一部分以限定其中优选围绕第一导电区域的上部的凹部。 然后在凹部中形成第二导电区域（例如Al，Cu，W，Ti，Ta和Co）。 这里，优选地选择第一导电区域以具有良好的阶梯覆盖能力以完全埋入接触孔，并且即使牺牲了某种程度的阶梯覆盖能力，优选将第二导电区域选择为具有非常低的电阻。 还可以执行平面化步骤（例如，CMP，回蚀刻）以限定接触孔中的第一导电区域并限定围绕第一导电区域的凹部中的第二导电区域。 阻挡金属层也可以在其中形成第一导电区域之前以及在其中形成第二导电区域之前在凹部中沉积在接触孔中。

    Method of manufacturing an electrical interconnection of a semiconductor device using an erosion protecting plug in a contact hole of interlayer dielectric layer
    6.
    发明授权
    Method of manufacturing an electrical interconnection of a semiconductor device using an erosion protecting plug in a contact hole of interlayer dielectric layer 有权
    使用层间电介质层的接触孔中的侵蚀保护插头制造半导体器件的电互连的方法

    公开(公告)号：US06372616B1

    公开(公告)日：2002-04-16

    申请号：US09670818

    申请日：2000-09-28

    申请人： Bong-young Yoo ,  Hyeon-deok Lee ,  Il-gu Kim

    发明人： Bong-young Yoo ,  Hyeon-deok Lee ,  Il-gu Kim

    IPC分类号： H01L213205

    CPC分类号： H01L21/76808

    摘要： A method of manufacturing an electrical interconnection of a semiconductor device produces an erosion protecting plug in a contact hole to protect a selected portion of an interlayer dielectric layer when the interlayer dielectric layer is being etched to form a recess for a conductive line. The contact hole is formed in the interlayer dielectric layer. The contact hole is filled with an organic material to form the erosion protecting plug. The organic material is a photoresist material or an organic polymer. A photoresist pattern is formed for exposing the erosion protecting plug and a portion of the interlayer dielectric layer adjacent to the erosion protecting plug. A recess which extends down to the contact hole is formed by etching the portion of the interlayer dielectric layer which is exposed by the photoresist pattern. The erosion protecting plug and the photoresist pattern are then removed. A conductive line filling the recess and a contact filling the contact hole are then formed.

    摘要翻译： 制造半导体器件的电互连的方法在接触孔中产生侵蚀保护插塞，以便在蚀刻层间电介质层以形成用于导电线的凹槽时保护层间电介质层的选定部分。 接触孔形成在层间电介质层中。 接触孔填充有机材料以形成侵蚀保护塞。 有机材料是光致抗蚀剂材料或有机聚合物。 形成光致抗蚀剂图案，用于暴露侵蚀保护塞和与侵蚀保护塞相邻的层间电介质层的一部分。 通过蚀刻由光致抗蚀剂图案曝光的层间电介质层的部分来形成向下延伸到接触孔的凹部。 然后去除侵蚀保护塞和光致抗蚀剂图案。 然后形成填充凹部的导电线和填充接触孔的触点。