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    Delayed-locked loop with fine and coarse control using cascaded phase interpolator and variable delay circuit
    2.
    发明授权
    Delayed-locked loop with fine and coarse control using cascaded phase interpolator and variable delay circuit 有权
    使用级联相位内插器和可变延迟电路的精细和粗略控制的延迟锁定环路

    公开(公告)号：US07046058B1

    公开(公告)日：2006-05-16

    申请号：US10671305

    申请日：2003-09-24

    申请人： Al Fang ,  Mike Farrell ,  Brian Butka

    发明人： Al Fang ,  Mike Farrell ,  Brian Butka

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0818

    摘要： A delay-locked loop (DLL) circuit includes a phase interpolator circuit and variable delay circuit coupled in cascade and operative to generate an output clock signal that is delayed with respect to a reference clock signal responsive to respective first and second control signals applied to the phase interpolator and the variable delay circuit. The DLL circuit further includes a phase control circuit that generates the first and second control signals responsive to the output clock signal and the reference clock signal. The variable delay circuit may provide a coarser resolution than the phase interpolator circuit, for example, the variable delay circuit may include a tapped delay chain circuit configured to provide step changes in delay responsive to the second control signal. The phase control circuit may be operative to cause the phase interpolator circuit to shift from one extreme of a delay range thereof towards another extreme of the delay range concurrent with a step change in delay through the variable delay circuit to thereby limit overcompensation.

    摘要翻译： 延迟锁定环路（DLL）电路包括相位内插器电路和可变延迟电路，其可级联耦合并且可操作以产生相对于参考时钟信号延迟的输出时钟信号，所述输出时钟信号响应于施加到所述第一和第二控制信号的相应的第一和第二控制信号 相位内插器和可变延迟电路。 该DLL电路还包括相位控制电路，该相位控制电路根据输出时钟信号和参考时钟信号产生第一和第二控制信号。 可变延迟电路可以提供比相位内插器电路更粗的分辨率，例如，可变延迟电路可以包括被配置为响应于第二控制信号提供延迟的延迟阶跃变化的抽头延迟链电路。 相位控制电路可操作以使相位内插器电路从其延迟范围的一个极端移向延迟范围的另一极端，并通过可变延迟电路与延迟的阶跃变化同步，从而限制过补偿。

    Impedance-matched output driver circuits having enhanced predriver control
    4.
    发明授权
    Impedance-matched output driver circuits having enhanced predriver control 有权
    具有增强的预驱动器控制的阻抗匹配输出驱动器电路

    公开(公告)号：US06967501B1

    公开(公告)日：2005-11-22

    申请号：US10739467

    申请日：2003-12-18

    申请人： Brian Butka

    发明人： Brian Butka

    IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/003 ,  H03K19/017

    CPC分类号： H03K17/164 ,  H03K19/0005 ,  H03K19/0027 ,  H03K19/01721

    摘要： Impedance-matched output driver circuits utilize predriver circuits with analog control to provide enhanced operating characteristics. This analog control may be provided by an analog loop containing differential amplifiers that set the resolution limit of the output driver circuit. These output driver circuits include a first PMOS pull-up transistor having source and drain terminals electrically connected in series in a pull-up path of the output driver circuit. An NMOS pass transistor has a first current carrying terminal electrically connected to a gate terminal of the first PMOS pull-up transistor and a second current carrying terminal configured to receive a P-type analog reference voltage (VP). This P-type reference voltage controls the conductivity of the first PMOS pull-up transistor in the pull-up path. A gate terminal of the NMOS pass transistor is responsive to a pull-up data input signal (DINP). A first NMOS pull-down transistor has source and drain terminals that are electrically connected in series in a pull-down path of the output driver circuit. A PMOS pass transistor is provided having a first current carrying terminal electrically connected to a gate terminal of the first NMOS pull-down transistor and a second current carrying terminal configured to receive an N-type analog reference voltage (VN). This N-type reference voltage controls the conductivity of the first NMOS pull-down transistor in the pull-down path. A gate terminal of the PMOS pass transistor is responsive to a pull-down data input signal (DINN).

    摘要翻译： 阻抗匹配的输出驱动器电路利用具有模拟控制的预驱动电路来提供增强的工作特性。 该模拟控制可以由包含设置输出驱动器电路的分辨率极限的差分放大器的模拟环路提供。 这些输出驱动器电路包括第一PMOS上拉晶体管，其具有在输出驱动器电路的上拉路径中串联电连接的源极和漏极端子。 NMOS传输晶体管具有电连接到第一PMOS上拉晶体管的栅极端子的第一载流端子和被配置为接收P型模拟参考电压（VP）的第二载流端子。 该P型参考电压控制上拉路径中第一PMOS上拉晶体管的电导率。 NMOS传输晶体管的栅极端子响应于上拉数据输入信号（DINP）。 第一NMOS下拉晶体管具有在输出驱动器电路的下拉路径中串联电连接的源极和漏极端子。 提供PMOS传输晶体管，其具有电连接到第一NMOS下拉晶体管的栅极端子的第一载流端子和被配置为接收N型模拟参考电压（VN）的第二载流端子。 该N型参考电压控制下拉路径中的第一NMOS下拉晶体管的电导率。 PMOS传输晶体管的栅极端子响应于下拉数据输入信号（DINN）。

    Impedance-matched output driver circuits having enhanced predriver control
    5.
    发明授权
    Impedance-matched output driver circuits having enhanced predriver control 有权
    具有增强的预驱动器控制的阻抗匹配输出驱动器电路

    公开(公告)号：US07053661B1

    公开(公告)日：2006-05-30

    申请号：US11207370

    申请日：2005-08-19

    申请人： Brian Butka

    发明人： Brian Butka

    IPC分类号： H03K19/094

    CPC分类号： H03K17/164 ,  H03K19/0005 ,  H03K19/0027 ,  H03K19/01721

    摘要： Impedance-matched output driver circuits utilize predriver circuits with analog control to provide enhanced operating characteristics. This analog control may be provided by an analog loop containing differential amplifiers that set the resolution limit of the output driver circuit. These output driver circuits include a first PMOS pull-up transistor having source and drain terminals electrically connected in series in a pull-up path of the output driver circuit. An NMOS pass transistor has a first current carrying terminal electrically connected to a gate terminal of the first PMOS pull-up transistor and a second current carrying terminal configured to receive a P-type analog reference voltage (VP). This P-type reference voltage controls the conductivity of the first PMOS pull-up transistor in the pull-up path. A gate terminal of the NMOS pass transistor is responsive to a pull-up data input signal (DINP). A first NMOS pull-down transistor has source and drain terminals that are electrically connected in series in a pull-down path of the output driver circuit. A PMOS pass transistor is provided having a first current carrying terminal electrically connected to a gate terminal of the first NMOS pull-down transistor and a second current carrying terminal configured to receive an N-type analog reference voltage (VN). This N-type reference voltage controls the conductivity of the first NMOS pull-down transistor in the pull-down path. A gate terminal of the PMOS pass transistor is responsive to a pull-down data input signal (DINN).

    摘要翻译： 阻抗匹配的输出驱动器电路利用具有模拟控制的预驱动电路来提供增强的工作特性。 该模拟控制可以由包含设置输出驱动器电路的分辨率极限的差分放大器的模拟环路提供。 这些输出驱动器电路包括第一PMOS上拉晶体管，其具有在输出驱动器电路的上拉路径中串联电连接的源极和漏极端子。 NMOS传输晶体管具有电连接到第一PMOS上拉晶体管的栅极端子的第一载流端子和被配置为接收P型模拟参考电压（VP）的第二载流端子。 该P型参考电压控制上拉路径中第一PMOS上拉晶体管的电导率。 NMOS传输晶体管的栅极端子响应于上拉数据输入信号（DINP）。 第一NMOS下拉晶体管具有在输出驱动器电路的下拉路径中串联电连接的源极和漏极端子。 提供PMOS传输晶体管，其具有电连接到第一NMOS下拉晶体管的栅极端子的第一载流端子和被配置为接收N型模拟参考电压（VN）的第二载流端子。 该N型参考电压控制下拉路径中的第一NMOS下拉晶体管的电导率。 PMOS传输晶体管的栅极端子响应于下拉数据输入信号（DINN）。