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公开(公告)号：US5942940A
公开(公告)日：1999-08-24
申请号：US897476
申请日：1997-07-21
IPC分类号： H03F3/45
CPC分类号： H03F3/45237 , H03F2203/45454
摘要： A CMOS differential amplifier uses a first pair of complementary MOSFETs and a second pair of complementary MOSFETs coupled to a power supply (by another pair of MOSFETs) in such a manner as to be self-biasing and have improved channel-length modulation characteristics. An N-type MOSFET couples the first and second complementary MOSFET pairs to ground potential via a first resistor, and a P-type MOSFET couples the first and second complementary MOSFET pairs to a power-supply via a second resistor. The first and second resistors can be provided using non-salicided N-type MOSFET resistors. The third N-type MOSFET preferably has a low-threshold voltage, including a zero-threshold voltage, and the substrates of the P-type MOSFETs in the first and second complementary pairs are further preferably connected to the sources of those MOSFETs in order to reduce body-sensitivity effects.
摘要翻译： CMOS差分放大器使用第一对互补MOSFET和第二对互补MOSFET，其以这样的方式耦合到电源（由另一对MOSFET），并且具有改善的沟道长度调制特性。 N型MOSFET通过第一电阻器将第一和第二互补MOSFET对耦合到地电位，并且P型MOSFET通过第二电阻将第一和第二互补MOSFET对耦合到电源。 第一和第二电阻可以使用非水银N型MOSFET电阻器来提供。 第三N型MOSFET优选地具有包括零阈值电压的低阈值电压，并且第一和第二互补对中的P型MOSFET的衬底进一步优选地连接到这些MOSFET的源极，以便 减少身体敏感性的影响。
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公开(公告)号：US06501313B2
公开(公告)日：2002-12-31
申请号：US09749335
申请日：2000-12-27
IPC分类号： H03K3017
CPC分类号： H03K5/1565
摘要： A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer. Alternatively, the invention may be implemented in an analog fashion, such as by applying an analog signal to the body contact, wherein the analog signal is generated using an asymmetric charge-pump and filter connected to the clock signal.
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公开(公告)号：US06014047A
公开(公告)日：2000-01-11
申请号：US4133
申请日：1998-01-07
CPC分类号： H03K5/135 , G06F1/04 , G06F1/10 , H03L7/0814 , H03L7/0991
摘要： Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.
摘要翻译： 在多个相对于其它信号相移的信号中，一个信号被重复地替换为另一个信号作为时钟信号，以减少时钟信号相对于参考时钟的相位误差。 这些替代被定时在间隔期间发生，以减少对时钟信号的干扰。 此外，信号的这种替换响应于由信号的直接前辈提供的时钟之后的信号的至少一个周期的发生，这倾向于防止一个信号被错误地替换为另一个信号。
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4.发明授权Clock generation apparatus and method for CMOS microprocessors using a differential saw oscillator 失效使用差分锯齿振荡器的CMOS微处理器的时钟产生装置和方法
公开(公告)号：US5870592A
公开(公告)日：1999-02-09
申请号：US742220
申请日：1996-10-31
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/18
摘要： A clock generation apparatus and method for generating clock signals for a microprocessor integrated circuit. The clock generation apparatus includes a device which generates a reference frequency, an acoustic wave oscillator having an oscillation frequency slightly faster than the reference frequency and a circuit configuration coupled to the acoustic wave oscillator which generates frequency bearing signals in response to an output of the acoustic wave oscillator. The frequency bearing signals carry negligible jitter. The circuit configuration includes a quadrature rotator for controlling clock phase, a clock distributor for efficiently dispersing clock signals to the microprocessor integrated circuit, a bus divider which provides a feedback clock signal phase aligned with the reference frequency, a phase detector for detecting the phase difference of a bus clock signal and the feedback clock signal, and a digital filter responsive to the phase detector.
摘要翻译： 一种用于产生微处理器集成电路的时钟信号的时钟产生装置和方法。 时钟发生装置包括产生参考频率的装置，振荡频率略高于参考频率的声波振荡器，以及耦合到声波振荡器的电路配置，该声波振荡器响应于声音的输出产生频率承载信号 波振荡器。 频率承载信号携带可忽略的抖动。 电路配置包括用于控制时钟相位的正交旋转器，用于有效地将时钟信号分散到微处理器集成电路的时钟分配器，提供与参考频率对准的反馈时钟信号相位的总线分频器，用于检测相位差的相位检测器 总线时钟信号和反馈时钟信号，以及响应于相位检测器的数字滤波器。
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公开(公告)号：US5949262A
公开(公告)日：1999-09-07
申请号：US004136
申请日：1998-01-07
摘要： A method and apparatus are provided for generating synchronized clock signals. According to the method and apparatus, first and second pluralities of signals are generated, having time-varying phase differences with respect to a reference clock. The first clock is supplied by a succession of signals from among the first plurality of signals, in which one of the signals succeeds another responsive to a first phase difference. The second clock is supplied by a second succession of signals from among the second plurality of signals. One signal in the second succession of signals succeeds another responsive to a second phase difference. The succession among the first plurality of signals is also responsive to the second phase difference.
摘要翻译： 提供了一种用于产生同步时钟信号的方法和装置。 根据该方法和装置，产生第一和第二多个信号，其相对于参考时钟具有时变相位差。 第一时钟由来自第一多个信号中的一系列信号提供，其中一个信号成功响应于第一相位差。 所述第二时钟由所述第二多个信号中的第二序列信号提供。 第二次信号中的一个信号成功响应于第二相位差。 第一组多个信号之间的相继也响应于第二相位差。
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6.发明申请Method for Performing Memory Diagnostics Using a Programmable Diagnostic Memory Module 失效使用可编程诊断内存模块执行内存诊断的方法公开(公告)号：US20090049341A1
公开(公告)日：2009-02-19
申请号：US11840498
申请日：2007-08-17
CPC分类号： G06F11/24
摘要： A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.
摘要翻译： 使用可编程诊断存储器模块执行存储器诊断的方法提供了存储器控制器和存储器子系统设计的增强的可测试性。 可编程诊断存储器模块包括用于与外部诊断系统通信的接口，并且该接口用于将命令传送到存储器模块以改变存储器模块的各种行为。 改变的行为可能是改变被写入存储器模块的数据流，以模拟错误，改变存储器模块信号的定时和/或加载，下载由存储器模块内的处理器核心执行的程序，改变驱动器的输出强度 存储器模块的信号和在模拟域中的操作，在存储器模块的端子处发出信号，例如在与存储器模块的电源连接上注入噪声。 存储器模块可以模拟多个可选择的存储器模块类型，并且可以包括完整的存储阵列以提供标准存储器模块操作。
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7.发明申请公开(公告)号：US20080175327A1
公开(公告)日：2008-07-24
申请号：US12058689
申请日：2008-03-29
IPC分类号： H04B3/00
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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公开(公告)号：US07362697B2
公开(公告)日：2008-04-22
申请号：US10339757
申请日：2003-01-09
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。
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9.发明授权Method and apparatus for supplying a reference voltage for chip-to-chip communication 有权用于提供用于芯片到芯片通信的参考电压的方法和装置公开(公告)号：US06891406B2
公开(公告)日：2005-05-10
申请号：US10339754
申请日：2003-01-09
CPC分类号： H04L25/06
摘要： A method for receiving data by an integrated circuitry chip includes receiving data signals and a first clock signal sent by a sending chip. The data signals are received by data receivers and the clock signal is received by at least one clock receiver of the receiving chip. A reference voltage is derived by reference voltage circuitry for the receiving chip responsive to the first clock signal. Logical states of the received data signals are detected. The detecting includes the data receivers comparing voltage levels of the received data signals to the derived reference voltage.
摘要翻译： 一种用于由集成电路芯片接收数据的方法包括接收由发送芯片发送的数据信号和第一时钟信号。 数据信号由数据接收器接收，时钟信号由接收芯片的至少一个时钟接收器接收。 参考电压由对应于第一时钟信号的接收芯片的参考电压电路导出。 检测出接收到的数据信号的逻辑状态。 该检测包括数据接收器，将接收的数据信号的电压电平与导出的参考电压进行比较。
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公开(公告)号：US06725304B2
公开(公告)日：2004-04-20
申请号：US09740248
申请日：2000-12-19
IPC分类号： G06F1342
CPC分类号： G06F13/4269
摘要： An apparatus for connecting circuit modules is disclosed. The apparatus for connecting circuit modules that receives an input and an output signal at one circuit module and uses a transmitter/receiver to transmit data to and receive data from the second circuit module. Each transmitter/receiver is selectable between a bidirectional mode that transmits and simultaneously receives via two transmission lines, and a unidirectional mode that transmits on a first transmission line and receives from a second transmission line.
摘要翻译： 公开了一种用于连接电路模块的装置。 用于连接在一个电路模块处接收输入和输出信号的电路模块的装置，并且使用发射机/接收机向第二电路模块发送数据和从第二电路模块接收数据。 每个发射机/接收机可以在通过两条传输线路发送和同时接收的双向模式之间进行选择;以及单向模式，其在第一传输线路上传输并从第二传输线路接收。
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