利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.013 秒)

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND FABRICATION SYSTEM OF SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND FABRICATION SYSTEM OF SEMICONDUCTOR DEVICE 失效
    半导体器件的制造方法和半导体器件的制造系统

    公开(公告)号：US20120003761A1

    公开(公告)日：2012-01-05

    申请号：US12828404

    申请日：2010-07-01

    申请人： Won Song ,  Byung-Goo Jeon

    发明人： Won Song ,  Byung-Goo Jeon

    IPC分类号： H01L21/66 ,  G06F19/00

    CPC分类号： H01L22/20 ,  H01L22/12 ,  Y10S438/949 ,  Y10S438/981

    摘要： A method of fabricating a semiconductor device and a fabrication system of the semiconductor device are provided. The method includes sequentially forming a film to be etched and a dielectric film and measuring a thickness of the dielectric film, forming a photoresist film on the dielectric film, performing a lithography process using the measured thickness of the dielectric film to form a photoresist film pattern, and etching the dielectric film and the film to be etched using the photoresist film pattern.

    摘要翻译： 提供一种半导体器件的制造方法和半导体器件的制造系统。 该方法包括顺序地形成待蚀刻的膜和电介质膜并测量电介质膜的厚度，在电介质膜上形成光致抗蚀剂膜，使用所测量的电介质膜的厚度进行光刻处理以形成光刻胶膜图案 并且使用光致抗蚀剂膜图案蚀刻电介质膜和待蚀刻的膜。

    Method of fabricating semiconductor device comprises a photoresist pattern having a desired critical dimension
    4.
    发明授权
    Method of fabricating semiconductor device comprises a photoresist pattern having a desired critical dimension 失效
    制造半导体器件的方法包括具有所需临界尺寸的光致抗蚀剂图案

    公开(公告)号：US08232199B2

    公开(公告)日：2012-07-31

    申请号：US12828404

    申请日：2010-07-01

    申请人： Won Song ,  Byung-Goo Jeon

    发明人： Won Song ,  Byung-Goo Jeon

    IPC分类号： H01L21/4763

    CPC分类号： H01L22/20 ,  H01L22/12 ,  Y10S438/949 ,  Y10S438/981

    摘要： A method of fabricating a semiconductor device and a fabrication system of the semiconductor device are provided. The method includes sequentially forming a film to be etched and a dielectric film and measuring a thickness of the dielectric film, forming a photoresist film on the dielectric film, performing a lithography process using the measured thickness of the dielectric film to form a photoresist film pattern, and etching the dielectric film and the film to be etched using the photoresist film pattern.

    摘要翻译： 提供一种半导体器件的制造方法和半导体器件的制造系统。 该方法包括顺序地形成待蚀刻的膜和电介质膜并测量电介质膜的厚度，在电介质膜上形成光致抗蚀剂膜，使用所测量的电介质膜的厚度进行光刻处理以形成光刻胶膜图案 并且使用光致抗蚀剂膜图案蚀刻电介质膜和待蚀刻的膜。

    Method of fabricating non-volatile memory device
    7.
    发明授权
    Method of fabricating non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US06897115B2

    公开(公告)日：2005-05-24

    申请号：US10643538

    申请日：2003-08-19

    申请人： In-Soo Cho ,  Jae-Min Yu ,  Byung-Goo Jeon ,  Jun-Yeoul You ,  Chang-Yup Lee

    发明人： In-Soo Cho ,  Jae-Min Yu ,  Byung-Goo Jeon ,  Jun-Yeoul You ,  Chang-Yup Lee

    IPC分类号： G11C7/00 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A method of fabricating a non-volatile memory device includes the steps of forming a lower conductive layer on a substrate, forming a lower and an upper sacrificial patterns on the substrate with the lower conductive layer, wherein the lower and upper sacrificial patterns include a trench exposing the lower conductive layer, forming mask spacers on sidewalls of the upper and lower sacrificial patterns, using the mask spacers and the upper sacrificial pattern as an etch mask, etching the exposed lower conductive layer to form a lower conductive pattern exposing the substrate, forming a plug conductive layer covering an entire surface of a substrate with the lower conductive pattern, and planarizingly etching the plug conductive layer until the lower sacrificial pattern is exposed, thereby forming a source plug in a gap region between the mask spacers that is connected to the substrate.

    摘要翻译： 一种制造非易失性存储器件的方法包括以下步骤：在衬底上形成下导电层，在下导电层上在衬底上形成下牺牲图形和上牺牲图案，其中下和下牺牲图案包括沟槽 暴露下导电层，使用掩模间隔物和上牺牲图案作为蚀刻掩模在上和下牺牲图案的侧壁上形成掩模间隔物，蚀刻暴露的下导电层以形成露出基板的下导电图案，形成 插入导电层，其覆盖具有下导电图案的基板的整个表面，并且平坦化地蚀刻插头导电层，直到下部牺牲图案露出为止，从而在连接到所述屏蔽间隔物之间​​的间隙区域中形成源极插塞 基质。